Online Verilog Compiler

Write, run, and share code snippets. No setup required.

main.v

Click Run to see the output here.

PlusargsRuntime parameters passed to the simulator. Read them in your testbench with $value$plusargs or $test$plusargs.

KeyValue

// 4-bit synchronous counter - DUT plus a small testbench.
// Edit the +PERIOD / +RUNTIME / +VERBOSE plusargs in the panel
// below and press Run. Output appears on the right; the Waveform
// tab plots the signals dumped by $dumpfile/$dumpvars.

module counter(
    input  wire       clk,
    input  wire       reset,
    output reg  [3:0] count
);
    always @(posedge clk or posedge reset) begin
        if (reset)
            count <= 4'b0;
        else
            count <= count + 1'b1;
    end
endmodule

module test;
    reg clk;
    reg reset;
    wire [3:0] count;

    integer period;    // half-period of the clock, in time units
    integer runtime;   // total simulation time
    reg     verbose;

    // Instantiate the device under test.
    counter dut(.clk(clk), .reset(reset), .count(count));

    // Free-running clock - the HDL idiom. Toggles every PERIOD time units.
    always #(period) clk = ~clk;

    // Print on every rising edge so stdout lines up with the waveform.
    always @(posedge clk) begin
        if (verbose)
            $display("t=%0t  count=%0d", $time, count);
    end

    initial begin
        // Make the Waveform tab work - VCD output is written here.
        $dumpfile("dump.vcd");
        $dumpvars(0, test);

        // Defaults; override from the plusargs panel below.
        if (!$value$plusargs("PERIOD=%d",  period))  period  = 5;
        if (!$value$plusargs("RUNTIME=%d", runtime)) runtime = 80;
        verbose = $test$plusargs("VERBOSE") != 0;

        clk   = 0;
        reset = 1;
        #(period * 2) reset = 0;
        #(runtime)    $finish;
    end
endmodule

Write, compile, and simulate Verilog HDL online

A free online Verilog compiler and simulator. Write Verilog or SystemVerilog modules, drive a testbench, press Run, and see stdout output plus a rendered VCD waveform. No install, no Vivado, no Quartus, no toolchain to set up. The editor opens with a clocked counter testbench so you can edit and Run in seconds.

Code compiles with Icarus Verilog (iverilog) and runs under vvp inside a sandboxed container, so you get real Verilog HDL semantics - clocked always blocks, non-blocking assignments, hierarchical module instantiation, $display, $finish. Add $dumpfile and $dumpvars to your testbench and the Waveform tab renders single-bit signals and multi-bit buses with a draggable cursor, transitions, and per-signal value pills. Plusargs (+KEY=VALUE / +FLAG) flow into your testbench through $value$plusargs and $test$plusargs, so you can sweep clock period, run length, and feature flags without editing the source.

What makes this Verilog compiler useful

Instant compile and simulate - write Verilog HDL, press Run, and see stdout and VCD waveforms in seconds.
Verilog and SystemVerilog syntax highlighting in the same editor engine VS Code uses, with module/endmodule scoping and keyword autocompletion.
Built-in waveform viewer: emit $dumpfile + $dumpvars from your testbench and the Waveform tab renders signals, buses, transitions, and a movable cursor with per-signal value pills.
Plusargs panel for testbench parameters: drive +CYCLES, +PERIOD, +VERBOSE through $value$plusargs / $test$plusargs and rerun without rewriting the source.

What you can build in the Verilog playground

Combinational logic - adders, multiplexers, ALUs - wired up in a testbench with $display checks and instant feedback.
Clocked sequential designs - counters, shift registers, finite state machines driven by always @(posedge clk), with VCD waveforms to inspect signal transitions.
Parameter sweeps: drive +CYCLES, +PERIOD, or +VERBOSE plusargs to change behavior between runs, the same way you would on the iverilog/vvp command line.

Online Verilog compiler FAQ

What is Verilog?

Verilog is a hardware description language (HDL) used to model and simulate digital circuits, from simple combinational gates up to full processors. You describe modules, wires, and registers in code, compile them with a Verilog compiler, and run a testbench to verify behavior. SystemVerilog is a superset of Verilog that adds verification features. The playground accepts both.

Is the online Verilog compiler free?

Yes, the Verilog compiler and simulator are free to use. No sign-up, no Vivado or Quartus license, and no toolchain to install - write a module and press Run.

Do I need Icarus Verilog or any EDA tool installed?

No. Your code compiles with iverilog and runs under vvp in a sandboxed container on the server. You write the Verilog source and press Run; the compiler and simulator handle the rest.

How do I view waveforms for my Verilog code?

Inside an initial block in your testbench, call $dumpfile("dump.vcd") and $dumpvars(0, your_module). After Run, the Waveform tab renders the signals - click anywhere on a trace to drop a cursor and read per-signal values at that time.

How do I write a Verilog testbench with plusargs?

Add rows in the Plusargs panel (e.g. CYCLES=10, VERBOSE) and they're passed to the simulator as +CYCLES=10 +VERBOSE on the command line. In your testbench, read them with $value$plusargs("CYCLES=%d", n) for integer values, or $test$plusargs("VERBOSE") for boolean flags. The default starter code shows both patterns.

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