Learn Verilog
A free, interactive online Verilog course. You write Verilog on every lesson, with AI hints when your simulation output doesn't match what you expected, and a free certificate when you finish.
1,265+ codders enrolled
90 lessons78 challenges534 quiz questions
- Beginner friendly
AI-assisted coding help
Hands-on interactive lessons
Audio narration on every lesson
Quizzes to test your knowledge
Free certificate of completion
Syllabus
Section 1
Fundamentals
Start sectionStartExpandCollapseBuild a strong foundation in digital design with core Verilog skillsIntroduction
5 lessons433Data Types
7 lessons753Number System
6 lessons646Operators Part 1
5 lessons535Operators Part 2
6 lessons647Modules
7 lessons755Assign And Gates
6 lessons648Half Adder Project
Project3 lessons1Procedural Blocks
6 lessons646Decision Making
6 lessons635Loops
6 lessons646Multiplexer Project
Project3 lessons1Timing And Delays
6 lessons645Testbench Basics
6 lessons645Traffic Light Controller
Project5 lessons1Final Challenges
3 lessons3UART
Project4 lessons1
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January 2026
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Promotion zoneEvery way to learn
Read, listen, test yourself, ask the AI, or look up anything you've already covered. Every lesson meets you where you are.
A variable is a named container that stores a value you can reference later in your program.
In Python, you create one by writing the name, an equals sign, then the value you want to store.
The value can change over time - reassigning the name simply points it to a new value.
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Certificate of CompletionPython Fundamentals
Add to LinkedInWhy learn Verilog with Coddy
- Write and simulate real Verilog in your browser. No Icarus, Vivado, or ModelSim install - each lesson compiles your Verilog module and runs the testbench server-side, then shows the simulation output and any compile errors instantly.
- Verilog as digital designers actually use it: modules and ports, wires vs. registers, gate primitives (AND/OR/NOT/XOR), blocking vs. non-blocking assignments, combinational and sequential always blocks, parameters, finite state machines, and testbenches with
$display,$monitor, and$dumpvars. The hardware description language foundations you need before touching an FPGA. - AI hints walk you through the parts of Verilog that trip everyone up - blocking vs. non-blocking inside always blocks, when to use
wirevs.reg, sized vs. unsized numbers, and the meaning ofxandzvalues - so you build the right mental model of hardware (not software) from lesson one. - Build real hardware projects, not just exercises - a half adder, a 2-to-1 and 4-to-1 multiplexer, a traffic light controller as an FSM, and a UART transmitter. Each project ships with its own testbench so you can see your design simulate end-to-end.
Frequently asked questions about learning Verilog
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