NewJourney
Learn Verilog
A free, interactive online Verilog course. You write Verilog on every lesson - modules and ports, wires and registers, gate primitives, always blocks, FSMs, and the testbench patterns digital designers actually use - with AI hints when your simulation output doesn't match what you expected, and a free certificate when you finish.
2,500+ codders enrolled
- Beginner friendly
AI-assisted coding help
Hands-on interactive lessons
Audio narration on every lesson
Quizzes to test your knowledge
Free certificate of completion
Syllabus
Section 1
Fundamentals
Start sectionStartExpandCollapseBuild a strong foundation in digital design with core Verilog skillsIntroduction
5 lessons433- 01What Is VerilogChallenge
- 02Hardware vs SoftwareQuiz
- 03Design Abstraction LevelsChallengeQuiz
- 04Your First ModuleChallengeQuiz
- 05CommentsChallengeQuiz
Data Types
7 lessons753- 01Wire TypeChallengeQuiz
- 02Reg TypeChallengeQuiz
- 03Integer And RealChallengeQuiz
- 04VectorsChallengeQuiz
- 05ArraysChallengeQuiz
- 06ParametersChallengeQuiz
- 07Recap - Declare SignalsChallenge
Number System
6 lessons646- 01Binary RepresentationChallengeQuiz
- 02Sized NumbersChallengeQuiz
- 03Unsized NumbersChallengeQuiz
- 04Negative NumbersChallengeQuiz
- 05Special Values X And ZChallengeQuiz
- 06Recap - Number FormatsChallenge
Operators Part 1
5 lessons535- 01Arithmetic OperatorsChallengeQuiz
- 02Modulo OperatorChallengeQuiz
- 03Comparison OperatorsChallengeQuiz
- 04Recap - Simple MathChallenge
- 05Bitwise OperatorsChallengeQuiz
Operators Part 2
6 lessons647- 01Logical OperatorsChallengeQuiz
- 02Reduction OperatorsChallengeQuiz
- 03Shift OperatorsChallengeQuiz
- 04Concatenation OperatorChallengeQuiz
- 05Conditional OperatorChallengeQuiz
- 06Recap - Operator ChallengeChallenge
Modules
7 lessons755- 01Module StructureChallengeQuiz
- 02Input And Output PortsChallengeQuiz
- 03Inout PortsChallengeQuiz
- 04Module InstantiationChallengeQuiz
- 05Port Mapping By NameChallengeQuiz
- 06Port Mapping By OrderChallengeQuiz
- 07Recap - Build A ModuleChallenge
Assign And Gates
6 lessons648- 01Continuous AssignmentChallengeQuiz
- 02Assign With OperatorsChallengeQuiz
- 03Built In Gate PrimitivesChallengeQuiz
- 04AND OR NOT GatesChallengeQuiz
- 05XOR XNOR GatesChallengeQuiz
- 06Recap - Logic Gate CircuitChallenge
Half Adder Project
Project3 lessons1- 01Writing The ModuleChallenge
- 02Designing The LogicProject
- 03Writing The TestbenchProject
Procedural Blocks
6 lessons646- 01Always BlockChallengeQuiz
- 02Initial BlockChallengeQuiz
- 03Sensitivity ListChallengeQuiz
- 04Blocking AssignmentChallengeQuiz
- 05Non Blocking AssignmentChallengeQuiz
- 06Recap - Always vs InitialChallenge
Decision Making
6 lessons635- 01If StatementChallengeQuiz
- 02If - ElseChallengeQuiz
- 03Recap - Simple ComparatorChallenge
- 04Case StatementChallengeQuiz
- 05Casex And CasezChallengeQuiz
- 06Recap - ALU DesignChallenge
Loops
6 lessons646- 01For LoopChallengeQuiz
- 02While LoopChallengeQuiz
- 03Repeat LoopChallengeQuiz
- 04Forever LoopChallengeQuiz
- 05Disable StatementChallengeQuiz
- 06Recap - Loop PatternsChallenge
Multiplexer Project
Project3 lessons1- 012 To 1 Mux DesignChallenge
- 024 To 1 Mux DesignProject
- 03Using Case StatementProject
Timing And Delays
6 lessons645- 01What Are DelaysChallengeQuiz
- 02Gate DelaysChallengeQuiz
- 03Assignment DelaysChallengeQuiz
- 04Timescale DirectiveChallengeQuiz
- 05Clock GenerationChallengeQuiz
- 06Recap - Timing ControlChallenge
Testbench Basics
6 lessons645- 01What Is A TestbenchChallengeQuiz
- 02Creating StimulusChallengeQuiz
- 03Display And MonitorChallengeQuiz
- 04Dumpfile And DumpvarsChallengeQuiz
- 05Using System TasksChallengeQuiz
- 06Recap - Full TestbenchChallenge
Traffic Light Controller
Project5 lessons1- 01Defining The StatesChallenge
- 02State Machine LogicProject
- 03Timing The TransitionsProject
- 04Writing The TestbenchProject
- 05Verifying The OutputProject
Final Challenges
3 lessons3- 014 Bit CounterChallenge
- 02Decoder DesignChallenge
- 03Shift RegisterChallenge
UART
Project4 lessons1- 01Bit counterChallenge
- 02State MachineProject
- 03Transmitter DesignProject
- 04TestbenchProject
Why learn Verilog with Coddy
- Write and simulate real Verilog in your browser. No Icarus, Vivado, or ModelSim install - each lesson compiles your Verilog module and runs the testbench server-side, then shows the simulation output and any compile errors instantly.
- Verilog as digital designers actually use it: modules and ports, wires vs. registers, gate primitives (AND/OR/NOT/XOR), blocking vs. non-blocking assignments, combinational and sequential always blocks, parameters, finite state machines, and testbenches with
$display,$monitor, and$dumpvars. The hardware description language foundations you need before touching an FPGA. - AI hints walk you through the parts of Verilog that trip everyone up - blocking vs. non-blocking inside always blocks, when to use
wirevs.reg, sized vs. unsized numbers, and the meaning ofxandzvalues - so you build the right mental model of hardware (not software) from lesson one. - Build real hardware projects, not just exercises - a half adder, a 2-to-1 and 4-to-1 multiplexer, a traffic light controller as an FSM, and a UART transmitter. Each project ships with its own testbench so you can see your design simulate end-to-end.
Frequently asked questions about learning Verilog
What is Verilog used for?
Verilog is a hardware description language (HDL) used to design and simulate digital circuits - FPGAs, ASICs, and the chips inside almost every modern device. Engineers describe hardware behavior in Verilog, simulate it to verify correctness, then synthesize it down to actual gates and flip-flops. It's the workhorse language at companies like Intel, AMD, NVIDIA, Apple, Qualcomm, and most FPGA shops.
Is Verilog hard to learn?
Verilog looks a lot like C, but the mental model is completely different - you're describing hardware that runs in parallel, not software that runs line by line. The syntax is easy; the hard part is thinking in terms of wires, registers, and clock edges instead of variables and function calls. The course introduces hardware thinking gradually, starting with simple combinational logic and building up to clocked always blocks, finite state machines, and full testbenches.
Verilog vs. VHDL - which should I learn?
Both are mainstream HDLs and do the same job. Verilog (and its successor SystemVerilog) dominates in the US semiconductor industry, big chip companies, and most modern verification flows. VHDL is more common in European industry, aerospace, and defense. If you don't have a specific employer in mind, Verilog is the safer first HDL - it's closer to C syntactically and has a larger ecosystem of free tools and open-source designs.
Do I need to know Verilog for FPGA work?
Yes - Verilog (or VHDL, or increasingly SystemVerilog) is how you describe what an FPGA actually does. Vendor tools like Vivado, Quartus, and Lattice Radiant all take Verilog/SystemVerilog as input. High-level synthesis (HLS) and visual tools exist, but anything beyond a toy project on an FPGA ends up being written or read in Verilog.
How long does it take to learn Verilog?
Verilog basics - modules, ports, wires, registers, operators, simple always blocks - take two to three weeks of daily practice. Becoming comfortable with finite state machines, testbenches, and the projects in this course (half adder, multiplexer, traffic light FSM, UART) usually takes another one to two months. The next step - running your designs on an actual FPGA board - is its own learning curve on top of the language itself.
Can I learn Verilog online for free?
Yes. The interactive Verilog course is free - full lessons, coding exercises, simulated testbenches, and a certificate. Verilog compiles and simulates server-side, so you don't need to install Icarus Verilog, Vivado, or any FPGA toolchain locally to start writing real HDL.
