Verilog Documentation
Concise, example-driven Verilog reference. Read the concept, see the code, then practice it in a Coddy journey.
Start a guided Verilog journeyGetting Started
- What Is Verilog?A plain-English introduction to Verilog - what it is, what it's used for, how it differs from a regular programming language, and why digital designers still reach for it after 40 years.
- Hardware vs SoftwareWhy Verilog feels disorienting after software languages: concurrency by default, time as a first-class concept, and statements that don't run in order.
- Install VerilogInstall Icarus Verilog and GTKWave to compile and simulate Verilog locally. Or skip the install and use the browser editor - either works for these docs.
- Your First ModuleWrite your first complete Verilog module from scratch - declaration, ports, a piece of combinational logic, and a testbench that drives it. Runnable in the browser.
- CommentsHow to write single-line and multi-line comments in Verilog, plus the documentation patterns digital designers use to keep modules readable as they grow.
Data Types & Numbers
- Wire and RegThe two main data types in Verilog - `wire` for continuous connections and `reg` for procedural storage - and the rule for choosing between them every time.
- Vectors and ArraysHow to declare multi-bit signals with `[7:0]`, slice them, combine them, and the difference between a packed vector and a memory array.
- ParametersHow to use `parameter` and `localparam` to define compile-time constants, parameterize widths and depths, and override values when you instantiate a module.
- Number LiteralsHow Verilog writes constants: sized vs unsized, the `'b` `'h` `'d` `'o` bases, signed numbers, underscores for readability, and the gotchas that bite beginners.
- X and Z ValuesVerilog signals have four possible values, not two. Here's what `x` (unknown) and `z` (high-impedance) actually mean in simulation, and how to debug them.
Operators
- OperatorsThe core operators in Verilog - arithmetic, comparison, logical, and the conditional `?:` - with the rules and gotchas around mixed widths and signedness.
- Bitwise & ReductionThe bit-level operators in Verilog - bitwise AND/OR/XOR, the inversion forms, and the reduction operators that collapse a whole vector to a single bit.
- Concatenation & ReplicationHow to glue signals together with `{}` and copy a pattern N times with `{N{...}}` - the indispensable Verilog operators for building wider buses out of pieces.
Modules & Structure
- Module PortsHow to declare module ports - input, output, and inout - the ANSI-style port list, and when an output should be `wire` vs `reg`.
- Module InstantiationHow to instantiate one module inside another, the difference between named and positional port connections, and the multiple-instance patterns you'll use to build real designs.
- Continuous AssignmentHow `assign` works - the always-true relationship it describes, what it can and can't drive, and the patterns it shines at compared to procedural code.
Procedural Blocks
- Always BlockHow `always` blocks work, the difference between combinational `always @(*)` and clocked `always @(posedge clk)`, and the rules that decide what hardware each produces.
- Initial BlockHow `initial` blocks differ from `always`, why they only exist in simulation, and the common patterns - stimulus, waveform setup, log headers - they're used for.
- Blocking vs Non-blockingThe single most-confused topic in beginner Verilog. What `=` and `<=` actually mean inside an `always` block, and the rule that prevents most race conditions.
Control Flow
- If-ElseHow `if`/`else` works inside an `always` block, the latch trap that catches beginners, and the priority-encoder hardware that chained `else if`s produce.
- Case StatementHow `case` works for clean multi-way decoding, the `default` you should never skip, and the differences between `case`, `casex`, and `casez`.
- For LoopsHow Verilog `for` loops differ from their software cousins - they're unrolled by the synthesizer into parallel hardware, not executed iteratively at runtime.
Sequential Logic & FSMs
- Clocked LogicHow to build registers, counters, shift registers, and pipelines from clocked `always` blocks - the workhorse pattern of every synchronous digital design.
- Finite State MachinesHow to write a Verilog FSM the way professionals do - a clocked state register, a combinational next-state block, and a clean separation that's easy to read and synthesize.
Testbenches & Simulation
- Testbench BasicsHow to write a Verilog testbench - clock generation, reset sequence, stimulus, observation, and the standard skeleton that drives every simulation you'll run.
- Display & MonitorHow `$display`, `$write`, and `$monitor` work - the format specifiers you'll use, the difference between them, and when each is the right tool.
- Dumpfile & VCDHow to add VCD waveform output to a testbench - `$dumpfile`, `$dumpvars`, scope selection, and how to view the resulting file in GTKWave or the browser editor.
- Timescale & DelaysHow the `` `timescale `` directive sets the unit of `#delay`, the rules for combining different units across files, and how delays interact with clocked logic.
