Verilog 在线编译器

点击运行，在这里查看输出。

// 4-bit synchronous counter - DUT plus a small testbench.
// Edit the +PERIOD / +RUNTIME / +VERBOSE plusargs in the panel
// below and press Run. Output appears on the right; the Waveform
// tab plots the signals dumped by $dumpfile/$dumpvars.

module counter(
    input  wire       clk,
    input  wire       reset,
    output reg  [3:0] count
);
    always @(posedge clk or posedge reset) begin
        if (reset)
            count <= 4'b0;
        else
            count <= count + 1'b1;
    end
endmodule

module test;
    reg clk;
    reg reset;
    wire [3:0] count;

    integer period;    // half-period of the clock, in time units
    integer runtime;   // total simulation time
    reg     verbose;

    // Instantiate the device under test.
    counter dut(.clk(clk), .reset(reset), .count(count));

    // Free-running clock - the HDL idiom. Toggles every PERIOD time units.
    always #(period) clk = ~clk;

    // Print on every rising edge so stdout lines up with the waveform.
    always @(posedge clk) begin
        if (verbose)
            $display("t=%0t  count=%0d", $time, count);
    end

    initial begin
        // Make the Waveform tab work - VCD output is written here.
        $dumpfile("dump.vcd");
        $dumpvars(0, test);

        // Defaults; override from the plusargs panel below.
        if (!$value$plusargs("PERIOD=%d",  period))  period  = 5;
        if (!$value$plusargs("RUNTIME=%d", runtime)) runtime = 80;
        verbose = $test$plusargs("VERBOSE") != 0;

        clk   = 0;
        reset = 1;
        #(period * 2) reset = 0;
        #(runtime)    $finish;
    end
endmodule