Verilog Operators: Arithmetic, Comparison, Logical, and Conditional

What "Operator" Means in Verilog

Operators take signal-bearing expressions and produce new signal-bearing expressions. a + b is hardware - the synthesizer turns it into an adder. a == b is hardware - it builds a comparator. None of this is "code that runs"; it's all "circuits the operator describes".

The full operator menu is small enough to memorize. This doc covers the arithmetic, comparison, logical, and conditional operators. Bitwise and Reduction covers the bit-level operators that don't have direct software analogs.

Arithmetic: + - * / %

module arithmetic;
    initial begin
        $display("17 +  5 = %0d", 17 + 5);
        $display("17 -  5 = %0d", 17 - 5);
        $display("17 *  5 = %0d", 17 * 5);
        $display("17 /  5 = %0d", 17 / 5);   // integer division: 3
        $display("17 %% 5 = %0d", 17 % 5);   // modulo: 2
        $display("-3 *  4 = %0d", -3 * 4);   // works with signed
        $finish;
    end
endmodule

Three things to know:

1. Division is integer division. 7/2 is 3, not 3.5. Verilog doesn't have a float type (well, real, but that's simulation-only).
2. Division and modulo are expensive in hardware. A /4 is fine (the synthesizer turns it into a right shift), but a /n for runtime-variable n builds a multi-cycle divider you almost never want.
3. Overflow wraps. Adding two N-bit unsigned values that exceed N bits truncates to N bits. If you want to capture the carry, declare the result one bit wider:

wire [7:0] a, b;
wire [8:0] sum = a + b;   // 9-bit sum captures carry out

Comparison: == != < > <= >=

module comparison;
    initial begin
        $display("5 ==  5 = %b", 5 == 5);
        $display("5 !=  3 = %b", 5 != 3);
        $display("5 <   3 = %b", 5 < 3);
        $display("5 >=  5 = %b", 5 >= 5);

        // Watch out: comparing with x produces x, not 0
        $display("1'bx == 1'b0 = %b", 1'bx == 1'b0);   // x
        $display("1'bx === 1'b0 = %b", 1'bx === 1'b0); // 0

        $finish;
    end
endmodule

All six comparison operators return a single-bit result: 1 if true, 0 if false, x if either operand has an x or z bit. To handle the x/z case, reach for === and !== (the case-equality operators) covered in X and Z Values.

<= here is the comparison operator (less-than-or-equal). The same characters also mean non-blocking assignment in a procedural block (q <= d). Context tells them apart: inside an expression it's a comparison; on the left of a value being assigned, it's the assignment. The overlap is confusing but unambiguous to the parser.

Logical: && || !

Logical operators treat their operands as booleans (anything non-zero is true, zero is false) and produce a single-bit result:

module logical;
    initial begin
        $display("(5 > 3) && (2 < 4) = %b", (5 > 3) && (2 < 4));
        $display("(5 > 3) || (2 > 4) = %b", (5 > 3) || (2 > 4));
        $display("!(5 > 3)           = %b", !(5 > 3));

        // Logical on multi-bit values: anything nonzero is "true"
        $display("4'b1100 && 4'b0011 = %b", 4'b1100 && 4'b0011);   // 1
        $display("4'b1100 || 4'b0000 = %b", 4'b1100 || 4'b0000);   // 1
        $finish;
    end
endmodule

The crucial distinction to internalize: logical && is not bitwise &.

4'b1100 && 4'b0011   // 1 (both are non-zero, logical AND is true)
4'b1100 &  4'b0011   // 4'b0000 (no bit positions are 1 in both)

Same for || vs |. Use logical in if conditions and ?: predicates; use bitwise when you want each bit position to AND/OR independently.

&& and || are short-circuit in the C sense: the right-hand side isn't evaluated if the result is already determined by the left. This matters for testbenches that check pointers or function calls; it rarely matters for synthesizable RTL where everything happens in parallel anyway.

The Conditional Operator: ?:

The ternary is your best friend for building muxes and conditional expressions:

module muxes;
    wire [3:0] a = 4'hA;
    wire [3:0] b = 4'hB;
    wire sel;

    // 2-to-1 mux:
    wire [3:0] out = sel ? a : b;

    // 4-to-1 mux as a chain of ?:
    reg [1:0] sel4;
    wire [3:0] in0, in1, in2, in3;
    wire [3:0] out4 = (sel4 == 2'd0) ? in0
                    : (sel4 == 2'd1) ? in1
                    : (sel4 == 2'd2) ? in2
                    : in3;

    initial begin
        $display("a=%h b=%h out=%h",  a, b, out);
        $finish;
    end
endmodule

The pattern cond ? a : b is a 1-bit-select 2-to-1 multiplexer in hardware. Chaining them is fine for 3- and 4-way selects, but past that a case statement (covered in Case Statement) is dramatically more readable.

The ?: operator is also the standard way to give a register a default value that you only override sometimes:

next_value = update ? new_data : next_value;

Width Rules: The Beginner Pitfall

Verilog's width rules for arithmetic operators are notoriously surprising. The short version:

• The width of the result is the maximum of the widths of the inputs.
• If the result is assigned to something wider, it gets zero-extended (or sign-extended if signed).
• The width of intermediate computations is also the result width, which means overflow happens in the intermediate.

module width_trap;
    reg [7:0]  a, b;
    reg [15:0] product;

    initial begin
        a = 8'd200;
        b = 8'd200;

        // a * b "should" be 40000 (fits in 16 bits)
        // but the multiply happens at 8 bits, overflows, then assigns
        product = a * b;
        $display("8-bit *: product = %0d (expected 40000)", product);

        // Fix: cast one operand to wider before multiplying
        product = {8'b0, a} * b;
        $display("widened: product = %0d", product);

        $finish;
    end
endmodule

The first multiplication overflows because the operand widths are both 8 bits, the result width is therefore 8 bits, and 40000 doesn't fit. The second works because we explicitly widened a before multiplying.

The fix-line techniques:

• Use the concatenation operator {8'b0, a} to zero-extend.
• Use $unsigned(a) or $signed(a) to influence interpretation.
• Cast intermediate expressions to wider widths when in doubt.

Operator Precedence

You won't memorize the table, but you'll lean on a few rules:

• *, /, % bind tighter than +, -.
• Comparison binds tighter than logical (&&, ||).
• The conditional operator ?: has very low precedence - usually need parens around its branches in larger expressions.
• When in doubt, parenthesize. The simulator doesn't charge by the character.

out = (mode == 2'd0) ? a + b : a - b;   // clearer with parens

What Comes Next

You've covered every operator that looks like its software cousin. The next doc - Bitwise and Reduction - handles the operators that don't have direct software analogs: bitwise AND/OR/XOR per bit, plus the reduction forms that collapse a whole vector to a single bit.