Verilog Case Statement: Multi-Way Decoding Done Right

The Multi-Way Branch

case is Verilog's flat dispatch construct. You give it an expression; it picks the matching branch:

case (expression)
    pattern_1: statement_1;
    pattern_2: statement_2;
    pattern_3: begin
        statement_3a;
        statement_3b;
    end
    default: default_statement;
endcase

It's structurally similar to C's switch, but:

• There's no break - each branch is implicitly terminated by the next one.
• Patterns can be vectors, not just integers.
• The synthesizer turns the whole thing into a flat mux (or a one-hot decoder when the patterns make it possible).

A Worked Example: 4-to-1 Mux

module mux4(
    input  wire [1:0] sel,
    input  wire [7:0] in0, in1, in2, in3,
    output reg  [7:0] out
);
    always @(*) begin
        case (sel)
            2'd0: out = in0;
            2'd1: out = in1;
            2'd2: out = in2;
            2'd3: out = in3;
            default: out = 8'bx;
        endcase
    end
endmodule

module test;
    reg [1:0] sel;
    wire [7:0] out;
    wire [7:0] a = 8'hA0, b = 8'hB0, c = 8'hC0, d = 8'hD0;

    mux4 dut(.sel(sel), .in0(a), .in1(b), .in2(c), .in3(d), .out(out));

    initial begin
        for (integer i = 0; i < 4; i = i + 1) begin
            sel = i[1:0];
            #1 $display("sel=%0d out=%h", sel, out);
        end
        $finish;
    end
endmodule

The case body has four explicit patterns plus a default. The synthesizer sees a 2-bit input mapped to one of four values and emits a 4-to-1 multiplexer. Clean, flat, fast.

Why You Need default

For combinational case, omitting default is the same trap as if without else: any unmatched input value leaves out unassigned, and the synthesizer infers a latch.

For a 2-bit sel, the patterns above cover all four possible values - so in theory default is redundant. In practice:

1. The synthesizer doesn't always prove that the cases are exhaustive.
2. The selector might be x or z in simulation, which doesn't match any explicit case.
3. Adding a new case later might leave the default behavior unspecified.

Always write default. For state machines and mux logic where you know the default is unreachable, assigning 'x:

default: out = 8'bx;

…tells the synthesizer "this is a don't-care, optimize freely" and surfaces a bright red x in simulation if the unreachable case does somehow get reached. That's the best of both worlds.

A State Machine in case

The classic use of case is the state-transition logic of a finite state machine:

module traffic_light(
    input  wire       clk,
    input  wire       reset,
    output reg  [1:0] light    // 00=red, 01=yellow, 10=green
);
    localparam RED    = 2'd0;
    localparam GREEN  = 2'd1;
    localparam YELLOW = 2'd2;

    reg [1:0] state;
    reg [3:0] timer;

    always @(posedge clk) begin
        if (reset) begin
            state <= RED;
            timer <= 4'd0;
        end else if (timer == 4'd0) begin
            case (state)
                RED:    begin state <= GREEN;  timer <= 4'd6; end
                GREEN:  begin state <= YELLOW; timer <= 4'd2; end
                YELLOW: begin state <= RED;    timer <= 4'd5; end
                default: begin state <= RED;   timer <= 4'd0; end
            endcase
        end else begin
            timer <= timer - 4'd1;
        end
    end

    always @(*) light = state;
endmodule

module test;
    reg clk = 0;
    reg reset = 1;
    wire [1:0] light;
    traffic_light dut(.clk(clk), .reset(reset), .light(light));

    always #5 clk = ~clk;

    initial begin
        #12 reset = 0;
        #200 $finish;
    end

    always @(posedge clk)
        $display("t=%0t light=%0d", $time, light);
endmodule

The case (state) block is the state-transition logic. Each branch decides what the next state is and how long to stay in it. default is unreachable here (we cover RED/GREEN/YELLOW exhaustively in the 2-bit space), but it's there as a safety net - if state somehow becomes 2'd3, the FSM resets cleanly to RED instead of latching.

Finite State Machines goes deeper on this pattern.

Multiple Patterns Per Branch

You can list several patterns sharing a single statement, separated by commas:

case (opcode)
    4'h0, 4'h1, 4'h2: result = a + b;
    4'h3, 4'h4:       result = a - b;
    4'h8:             result = a & b;
    default:          result = 8'd0;
endcase

That's two opcodes both meaning "subtract", three meaning "add". The synthesizer ORs the patterns together for the comparator.

casez and casex: Don't-Care Matching

Sometimes you want to match a pattern with some bits unspecified - "any opcode that starts with 010":

casez (opcode)
    8'b010?_????: instruction = ALU_OP;
    8'b110?_????: instruction = LOAD_OP;
    8'b1110_????: instruction = JUMP_OP;
    default:      instruction = UNKNOWN;
endcasez

casez treats ? (and z) in the pattern as don't-cares. Each ? matches 0 or 1. Useful for decoding instruction formats where some bit positions are unused for certain opcode classes.

casex extends this to treat x as a don't-care too. casex is dangerous because uninitialized signals (which are x in simulation) match every case, producing surprising behavior. Most modern style guides recommend casez and forbid casex.

In SystemVerilog you also get case inside, which is the cleanest version of all - it accepts ranges and lists - but plain Verilog stops at casez.

case vs if/else if Chain

The two constructs can both express multi-way decisions, but they synthesize to different hardware:

• case is a flat dispatch. The synthesizer can produce a one-hot decoder, a balanced mux tree, or other flat structures. Constant time to evaluate.
• if/else if is a priority chain. The synthesizer produces a cascade where each level adds delay. Logarithmically slower.

Functionally they overlap. Stylistically: use case whenever the conditions are about the value of a single expression. Use if/else if when there's a true priority or when conditions involve different signals.

// Better as case:
if      (sel == 2'd0) out = a;
else if (sel == 2'd1) out = b;
else if (sel == 2'd2) out = c;
else                  out = d;

// Better as if/else if:
if      (urgent_event)  next_state = HANDLE_URGENT;
else if (timer_expired) next_state = TIMEOUT;
else if (data_ready)    next_state = PROCESS;
else                    next_state = state;

The first three conditions are all "what is sel?" - a case reads more naturally and synthesizes flatter. The second three are independent events with an obvious priority - if/else if is the better fit.

What Comes Next

The last doc in this chapter - For Loops - covers Verilog's for and the surprising thing that happens when you use it in synthesizable code. Then we move into sequential logic and FSMs in earnest.