What Is Verilog? A Beginner's Guide to the Hardware Description Language

A Language for Describing Circuits

Most languages you've met - Python, JavaScript, Go - describe a sequence of instructions for a CPU to execute. Verilog describes a circuit. You write down what wires exist, what registers exist, and how signals flow between them. A simulator can then play back the circuit's behavior, and a synthesis tool can compile the same text into the gates and flip-flops of a real chip.

That's the one-line definition. The implications take longer to absorb.

module hello;
    initial begin
        $display("hello from verilog");
        $finish;
    end
endmodule

That snippet looks like a tiny program: a module, an initial block, a $display system task. Press Run and you'll see hello from verilog. Under the hood, though, the simulator isn't executing a function - it's pretending time is passing and stepping the circuit forward. That's why you'll see $finish everywhere: somebody has to tell the simulator to stop.

What "Hardware Description" Actually Means

A line of C runs when the program counter reaches it. A line of Verilog describes a piece of circuitry that exists always. Consider:

assign y = a & b;

That's not "compute y once." It's "there is a wire y, and at every moment in time it equals a AND b." Change a or b and y follows immediately. Several assign statements in a module aren't a sequence - they're parallel descriptions of separate pieces of the circuit.

This is the defining feature of Verilog and the source of every beginner bug. Most of what you write describes things happening concurrently, and the few constructs that look like ordered statements (inside initial and always blocks) only look that way because the simulator pretends.

What You Build With Verilog

You'll see Verilog used at every level of the digital stack:

• Combinational logic. Adders, multiplexers, decoders, ALU slices - anything where the output depends only on the current inputs.
• Sequential logic. Counters, shift registers, finite state machines, anything clocked by a posedge clk.
• Processor cores. From homework CPUs in university courses to the open-source RISC-V cores shipping in real silicon, the RTL is usually Verilog or SystemVerilog.
• FPGA designs. Logic that gets loaded into a Xilinx or Intel FPGA - networking, image processing, embedded control - is overwhelmingly written in Verilog.
• ASICs. The custom chips inside your phone, your router, your car - the front-end design is HDL, and Verilog is one of the two dominant choices.

You don't need any of this hardware to learn. Everything in these docs runs in a browser-based simulator.

Simulation vs Synthesis

There are two ways to "run" Verilog, and they're not the same:

• Simulation plays the circuit's behavior in software. The simulator (Icarus Verilog, Verilator, ModelSim, commercial tools) reads your modules plus a testbench - code that drives the inputs - and produces output: text logs, waveforms, pass/fail reports.
• Synthesis takes a subset of Verilog and compiles it into a netlist of real gates. A vendor tool (Vivado, Quartus, design-compiler tools at large companies) handles the mapping. Synthesized Verilog has to obey extra rules - initial blocks and $display calls don't exist in silicon.

The browser editor on these pages does simulation. That's all you need until you're shipping a real chip or programming an FPGA.

Verilog vs SystemVerilog

If you go looking, you'll see both names. SystemVerilog is a superset - it keeps every Verilog construct and adds features mostly aimed at verification (classes, constrained-random testing, assertions, interfaces, a much richer type system). Anything you learn here is valid SystemVerilog. The two names blur together in practice; most tools accept both and most files end in .v regardless. We'll say "Verilog" throughout these docs.

Verilog vs VHDL

Both are hardware description languages. Both are IEEE standards. Both have been around since the 1980s. The differences:

• Syntax. Verilog descends from C - braces, terse keywords, looser type rules. VHDL descends from Ada - more verbose, much stricter about types.
• Geography. Verilog dominates in US-based commercial design. VHDL is still common in Europe, in defense work, and in older codebases.
• Capability. They're roughly equivalent in what they can express. Choose based on what your team uses.

If you're learning HDL for the first time, Verilog has the gentler ramp - smaller syntax, more permissive, and the standard library of examples online is bigger.

How These Docs Run Verilog

The editor below uses Icarus Verilog (iverilog) under the hood. It compiles your source into a simulator and runs it inside a sandbox. There's no Vivado license, no Quartus install, no FPGA board required. You write a module plus a small testbench, press Run, and you see the output and the waveform.

module counter(input wire clk, input wire reset, output reg [3:0] count);
    always @(posedge clk) begin
        if (reset) count <= 0;
        else       count <= count + 1;
    end
endmodule

module test;
    reg clk = 0;
    reg reset = 1;
    wire [3:0] count;

    counter dut(.clk(clk), .reset(reset), .count(count));

    always #5 clk = ~clk;

    initial begin
        $dumpfile("dump.vcd");
        $dumpvars(0, test);
        #12 reset = 0;
        #80 $finish;
    end

    always @(posedge clk) $display("t=%0t count=%0d", $time, count);
endmodule

That's a complete 4-bit counter plus a testbench. The counter module is the design under test (DUT); the test module wiggles the clock, releases reset, and prints the value every cycle. Run it and you'll see count walk from 0 to 15 and wrap. Open the Waveform tab and you'll see the same thing as voltage transitions.

What Comes Next

You have enough context to start writing modules. The next doc - Hardware vs Software - spends a little more time on the mental model shift, because it's the single biggest stumble for new Verilog programmers. After that, installing a local simulator (optional - the browser is fine), writing your first module from scratch, and the rest of the language.

Pace yourself. The syntax is small; the mental model is the work.