Verilog If-Else: Conditional Logic in Procedural Blocks

Familiar Syntax, Different Mental Model

if/else looks exactly like C:

if (condition) begin
    // ... statements ...
end else begin
    // ... statements ...
end

But the rules are different because Verilog isn't software. Two things to keep in mind:

1. if/else only lives inside a procedural block. You can't write a free-standing if at the module level.
2. What the if/else synthesizes to depends on the block type. In a combinational block, it becomes a multiplexer or priority encoder. In a clocked block, it becomes a flip-flop with conditional update logic.

Inside a Combinational Block

module max_of_three(
    input  wire [7:0] a,
    input  wire [7:0] b,
    input  wire [7:0] c,
    output reg  [7:0] max
);
    always @(*) begin
        if (a >= b && a >= c)
            max = a;
        else if (b >= c)
            max = b;
        else
            max = c;
    end
endmodule

module test;
    reg [7:0] a, b, c;
    wire [7:0] max;
    max_of_three dut(.a(a), .b(b), .c(c), .max(max));

    initial begin
        a = 8'd10; b = 8'd20; c = 8'd15; #1 $display("max(%0d,%0d,%0d)=%0d", a, b, c, max);
        a = 8'd50; b = 8'd30; c = 8'd40; #1 $display("max(%0d,%0d,%0d)=%0d", a, b, c, max);
        a = 8'd5;  b = 8'd5;  c = 8'd50; #1 $display("max(%0d,%0d,%0d)=%0d", a, b, c, max);
        $finish;
    end
endmodule

The combinational always @(*) block re-runs whenever a, b, or c changes. The if/else chain picks one branch, assigns max, and the block finishes. Since max is always assigned (every path has an assignment), the synthesizer produces pure combinational logic - no latch.

Note that max is declared reg even though there's no flip-flop in the hardware. Same rule as always: anything assigned inside always must be reg.

The Latch Trap

This is the single most common bug in beginner combinational code:

// WRONG - infers a latch
always @(*) begin
    if (enable)
        out = data;
    // no else! when `enable` is low, what does `out` do?
end

The synthesizer reads "when enable is low, out isn't assigned" and decides out has to remember its previous value. Remembering a value requires a storage cell, so the tool inserts a latch. Latches in synchronous designs cause timing problems, are hard to reset, and are almost never what you meant.

Two ways to fix it:

// Fix 1: explicit else branch
module no_latch_1(
    input  wire       enable,
    input  wire [7:0] data,
    output reg  [7:0] out
);
    always @(*) begin
        if (enable) out = data;
        else        out = 8'd0;
    end
endmodule

// Fix 2: default assignment at the top
module no_latch_2(
    input  wire       enable,
    input  wire [7:0] data,
    output reg  [7:0] out
);
    always @(*) begin
        out = 8'd0;             // default first
        if (enable) out = data; // override if condition holds
    end
endmodule

module test;
    reg en;
    reg [7:0] d;
    wire [7:0] out1, out2;

    no_latch_1 u1(.enable(en), .data(d), .out(out1));
    no_latch_2 u2(.enable(en), .data(d), .out(out2));

    initial begin
        en = 0; d = 8'h55; #1 $display("en=%b d=%h out1=%h out2=%h", en, d, out1, out2);
        en = 1; d = 8'hAA; #1 $display("en=%b d=%h out1=%h out2=%h", en, d, out1, out2);
        $finish;
    end
endmodule

Both produce the same combinational hardware - a 2-to-1 mux. The "default at the top" pattern scales better when you have lots of conditional assignments to the same signal.

Inside a Clocked Block

module counter_with_reset(
    input  wire       clk,
    input  wire       reset,
    input  wire       enable,
    output reg  [7:0] count
);
    always @(posedge clk) begin
        if (reset)        count <= 8'd0;
        else if (enable)  count <= count + 8'd1;
        // else: implicit hold (count keeps its value - that's what a flip-flop does)
    end
endmodule

module test;
    reg clk = 0;
    reg reset = 1;
    reg enable = 0;
    wire [7:0] count;

    counter_with_reset dut(.clk(clk), .reset(reset), .enable(enable), .count(count));

    always #5 clk = ~clk;

    initial begin
        #12 reset = 0;
        #5  enable = 1;
        #50 enable = 0;
        #20 enable = 1;
        #30 $finish;
    end

    always @(posedge clk)
        $display("t=%0t reset=%b enable=%b count=%0d", $time, reset, enable, count);
endmodule

Notice what's different from the combinational case:

• The block is always @(posedge clk) - flip-flop territory.
• Assignment uses <= (non-blocking).
• There's no else for the "neither reset nor enable" case. That's fine. In a clocked block, when no branch fires, the flip-flop simply holds its previous value - which is exactly what a flip-flop physically does. No latch is inferred because the signal already is a register.

This is the one place where omitting an else is safe. Outside of clocked blocks, always handle every path.

Chained else if: A Priority Encoder

A chain of else if statements has implicit priority - earlier conditions outrank later ones:

module priority_encoder(
    input  wire [3:0] requests,
    output reg  [1:0] grant,
    output reg        any
);
    always @(*) begin
        any = |requests;
        if      (requests[0]) grant = 2'd0;
        else if (requests[1]) grant = 2'd1;
        else if (requests[2]) grant = 2'd2;
        else if (requests[3]) grant = 2'd3;
        else                  grant = 2'd0;
    end
endmodule

module test;
    reg [3:0] req;
    wire [1:0] grant;
    wire any;
    priority_encoder dut(.requests(req), .grant(grant), .any(any));

    initial begin
        req = 4'b0000; #1 $display("req=%b any=%b grant=%0d", req, any, grant);
        req = 4'b0010; #1 $display("req=%b any=%b grant=%0d", req, any, grant);
        req = 4'b1010; #1 $display("req=%b any=%b grant=%0d", req, any, grant);
        req = 4'b1111; #1 $display("req=%b any=%b grant=%0d", req, any, grant);
        $finish;
    end
endmodule

requests[0] is the highest priority - if it's set, the grant is 0 regardless of what the higher-numbered bits do. The synthesizer turns the chain into a cascaded mux: check bit 0 first, then bit 1, then bit 2, then bit 3. Each level adds a small amount of delay.

If the conditions are mutually exclusive - say, decoding a one-hot input - a case statement (next doc) produces flatter, faster hardware than an else if chain. Use the case form when there's no genuine priority requirement.

if Without else in Clocked Code

A clocked block doesn't need an else because "hold the previous value" is the default. That's how you build enables:

always @(posedge clk) begin
    if (load) target <= incoming;
    // no else: when load is low, target keeps its value
end

That's a load-enabled register. Most pipeline registers, counters, and configuration registers use this pattern.

begin/end and Single Statements

Like C, you can omit begin/end for a single statement:

if (a) out = 1;
else   out = 0;

For anything past one statement, use the block:

if (a) begin
    out = 1;
    flag = 1;
end else begin
    out = 0;
    flag = 0;
end

The two patterns mix freely. Style guides generally recommend always using begin/end to make adding a second statement painless.

What Comes Next

The next doc - Case Statement - covers case, which is the right tool for multi-way decoding (state machines, opcode dispatch, ROM tables). After that, for loops, which are subtly different from their software cousins because they're unrolled at elaboration time.