Verilog Wire vs Reg: When to Use Each (with Examples)

Two Names, One Job

Every signal in Verilog has a type. The two types you'll meet first are wire and reg. Both can hold a value. Both can be single-bit or multi-bit. The difference isn't about what the signal is - it's about who drives it.

• wire signals are driven outside procedural blocks - by assign statements, by the outputs of sub-modules, or by module input ports.
• reg signals are driven inside procedural blocks - initial or always.

That's the entire rule. The keyword names are awkward because they predate the modern way of writing Verilog. reg doesn't always become a register in hardware. Read on for why.

Wire: The Continuous Connection

A wire is an electrical wire. It carries whatever its driver is producing, continuously. Two ways a wire gets driven:

module wires(input wire a, input wire b, output wire y, output wire z);
    // Driven by a continuous assignment.
    assign y = a & b;

    // Driven by a sub-module output - shown for completeness.
    // (the actual sub-module is omitted here)
    assign z = a | b;
endmodule

module test;
    reg a, b;
    wire y, z;

    wires dut(.a(a), .b(b), .y(y), .z(z));

    initial begin
        for (integer i = 0; i < 4; i = i + 1) begin
            {a, b} = i[1:0];
            #1 $display("a=%b b=%b y=%b z=%b", a, b, y, z);
        end
        $finish;
    end
endmodule

Three things to notice:

• y and z are declared wire in the module and wire again in the testbench.
• They're driven by assign - that's the continuous-assignment form. The right-hand side of the = is recomputed whenever any signal in it changes.
• We can't write y = a & b inside an always block while keeping y as wire. The compiler would reject it.

If you forget the wire keyword, Verilog will implicitly declare the signal as a single-bit wire for you - which is sometimes convenient and sometimes a silent bug. Most teams enable a tool option that errors on implicit wires. Be explicit and avoid the trap.

Reg: Storage Inside a Procedural Block

A reg is a signal you assign to inside initial or always. The name is a relic of the language's early days when "reg" sounded like "register"; in modern usage a reg is just the type of any signal procedural code writes to.

module regs(input wire clk, input wire reset, output reg [3:0] count);
    always @(posedge clk) begin
        if (reset) count <= 0;
        else       count <= count + 1;
    end
endmodule

module test;
    reg clk = 0;
    reg reset = 1;
    wire [3:0] count;

    regs dut(.clk(clk), .reset(reset), .count(count));

    always #5 clk = ~clk;

    initial begin
        #12 reset = 0;
        #80 $finish;
    end

    always @(posedge clk) $display("t=%0t count=%0d", $time, count);
endmodule

count is reg inside the module (because the always block writes to it) and wire in the testbench (because the DUT's output port drives it). Same signal, different roles, different types in each scope.

Why "Reg" Doesn't Always Mean "Register"

Here's the most common beginner trap. This module declares y as reg - but the synthesized hardware doesn't contain a flip-flop:

module not_a_register(input wire a, input wire b, output reg y);
    always @(*) begin
        y = a & b;
    end
endmodule

module test;
    reg a, b;
    wire y;

    not_a_register dut(.a(a), .b(b), .y(y));

    initial begin
        for (integer i = 0; i < 4; i = i + 1) begin
            {a, b} = i[1:0];
            #1 $display("a=%b b=%b y=%b", a, b, y);
        end
        $finish;
    end
endmodule

The always @(*) block is sensitive to any input change. It's combinational. A synthesis tool sees that pattern and produces an AND gate - no flip-flop, no clock, just logic. The reg keyword is purely a syntactic requirement because y is assigned inside an always.

To get an actual flip-flop, the always block has to be sensitive to a clock edge:

always @(posedge clk) begin
    q <= d;
end

That's the synthesis-tool-please-make-a-flip-flop pattern: clocked sensitivity list, non-blocking assignment. Same reg keyword, completely different hardware. We cover the distinction in Always Block and Blocking vs Non-blocking.

The Decision in Practice

Every time you declare a signal, ask: how will I drive it?

• Driving with assign? → wire.
• Connecting to a sub-module's output port? → wire.
• Module input port? → wire. (Inputs are always wire.)
• Driving from initial or always? → reg.
• Module output port driven by procedural code? → output reg.
• Module output port driven by assign? → output wire. (Or just output - direction alone defaults to wire.)

That decision tree covers every situation you'll meet in plain Verilog.

Driver Conflicts

wire signals can have multiple drivers in theory - that's how tri-state buses work, where several modules can drive the same wire and the inactive ones go high-impedance (z). For ordinary logic, two assign statements writing the same wire produce undefined behavior:

assign y = a;
assign y = b;   // BAD - y has two drivers

The simulator might pick one, might X-out the signal, depends on the tool. Either way it's a bug. One driver per wire unless you're explicitly building a bus.

reg signals can only be driven from one procedural block. Two always blocks both assigning the same reg is a synthesis error and bizarre in simulation. Same rule: one driver.

The SystemVerilog Update: logic

SystemVerilog (the superset Verilog evolved into) adds a single keyword that replaces both: logic. A logic signal can be driven by assign or by a procedural block - but not both - and the compiler stops you from accidentally setting up a multi-driver bug.

module modern(input logic a, input logic b, output logic y);
    assign y = a ^ b;
endmodule

If you're starting a project from scratch and your tool supports SystemVerilog (which the editor on this page does, with -g2012), using logic everywhere simplifies the rules. Plain .v files still need the wire/reg split, and you'll see both styles in the wild forever.

What Comes Next

The next doc - Vectors and Arrays - takes the same two types and shows how to make them multi-bit. Bus widths, ranges, packed dimensions, the difference between a vector of bits and an array of vectors. All the things you need before you can build anything bigger than a one-bit adder.