Verilog Bitwise and Reduction Operators

Two Roles for the Same Symbol

&, |, ^, and their inverted siblings show up in two distinct shapes:

• Binary form (two operands): a & b - bitwise operation between equally-wide vectors.
• Unary form (one operand): &a - reduction across all the bits of a to a single bit.

The compiler tells them apart by counting operands. The naming convention people use is "the bitwise operators" for the binary form and "the reduction operators" for the unary form.

Bitwise: One Bit at a Time

module bitwise;
    wire [7:0] a = 8'b1100_1010;
    wire [7:0] b = 8'b0101_1100;

    initial begin
        $display("a    = %b", a);
        $display("b    = %b", b);
        $display("a & b = %b", a & b);   // bitwise AND
        $display("a | b = %b", a | b);   // bitwise OR
        $display("a ^ b = %b", a ^ b);   // bitwise XOR
        $display("~a    = %b", ~a);      // bitwise NOT (one operand)
        $display("a ~^ b = %b", a ~^ b); // bitwise XNOR
        $finish;
    end
endmodule

The full set:

Operator	Name	Output bit at position N
a & b	AND	a[N] AND b[N]
a | b	OR	a[N] OR b[N]
a ^ b	XOR	a[N] XOR b[N]
a ~& b	NAND	NOT (a[N] AND b[N])
a ~| b	NOR	NOT (a[N] OR b[N])
a ~^ b	XNOR	NOT (a[N] XOR b[N])
~a	NOT	NOT a[N]

Note that ~&, ~|, ~^ are spelled with the tilde first and the operator second. They're a single token; there's no space between.

When the two operands have different widths, the narrower one is zero-extended on the left to match. If you want sign-extension, use signed operands explicitly with $signed().

Reduction: From Many Bits to One

The unary forms of the same operators collapse a vector to a single bit:

module reduction;
    wire [7:0] data1 = 8'b1111_1111;
    wire [7:0] data2 = 8'b0000_0001;
    wire [7:0] data3 = 8'b0101_0101;
    wire [7:0] data4 = 8'b0000_0000;

    initial begin
        $display("data = %b   &data  |data  ^data  $isunknown", data1);
        $display("       %b      %b     %b     %b", data1, &data1, |data1, ^data1);
        $display("       %b      %b     %b     %b", data2, &data2, |data2, ^data2);
        $display("       %b      %b     %b     %b", data3, &data3, |data3, ^data3);
        $display("       %b      %b     %b     %b", data4, &data4, |data4, ^data4);
        $finish;
    end
endmodule

What each one means:

• &data returns 1 if all bits of data are 1, otherwise 0. Useful for "is this all-ones?" checks.
• |data returns 1 if any bit of data is 1, otherwise 0. Useful for "is this non-zero?" checks.
• ^data returns the parity - XOR of all bits. 1 if odd count of 1s, 0 if even.
• ~&data, ~|data, ~^data are the inverses of the above.

You'll see these everywhere in real code:

wire empty       = ~|fifo_count;       // empty iff count is zero
wire all_ones    = &mask;              // all bits set
wire parity_bit  = ^data;              // parity of a byte
wire any_request = |request_vector;    // is anything requested?

The reduction forms are concise and synthesize to obvious gate trees: & reduces to a multi-input AND gate, | to a multi-input OR, ^ to an XOR tree (which is also the parity generator in hardware).

Common Patterns

Setting and Clearing Bits

wire [7:0] data;
wire [7:0] mask = 8'b0000_1000;

wire [7:0] set     = data | mask;     // forces bit 3 to 1
wire [7:0] cleared = data & ~mask;    // forces bit 3 to 0
wire [7:0] toggled = data ^ mask;     // flips bit 3
wire [7:0] tested  = data & mask;     // zero if bit 3 was 0, non-zero otherwise

These are the same bit-manipulation idioms you'd use in C. They synthesize to single-gate operations.

Checking If a Value Equals All Ones

wire is_max = &counter;       // 1 if every bit of counter is 1

A reduction AND with one gate, vs writing out counter == 8'hFF (which would also work; synthesizers usually produce identical hardware).

Generating a Parity Bit

module parity_demo;
    reg  [7:0] data;
    wire       parity = ^data;          // even parity bit
    wire       odd_parity = ~^data;     // odd parity bit

    initial begin
        for (integer i = 0; i < 8; i = i + 1) begin
            data = 8'd1 << i;
            #1 $display("data=%b parity=%b odd=%b", data, parity, odd_parity);
        end
        $finish;
    end
endmodule

Detecting Any Active Signal

wire any_pending = |request_vector;

If request_vector is wide (say 64 requesters), the reduction OR collapses to a single signal you can feed into a priority encoder or arbiter.

Shift Operators

While we're on bit-level operators, the shifts:

• a << N shifts a left by N bit positions, filling with zeros on the right.
• a >> N shifts a right by N bit positions, filling with zeros on the left.
• a <<< N arithmetic left shift (same as << for unsigned).
• a >>> N arithmetic right shift - fills with the sign bit when a is signed.

module shifts;
    initial begin
        $display("8'b0011_1100 << 2 = %b", 8'b0011_1100 << 2);
        $display("8'b0011_1100 >> 2 = %b", 8'b0011_1100 >> 2);

        // Arithmetic right shift on signed value preserves sign:
        $display("8'sb1100_0000 >>> 2 = %b", $signed(8'sb1100_0000) >>> 2);
        $finish;
    end
endmodule

Shifts by a constant power are free in hardware (just rewiring). Shifts by a runtime variable produce a barrel shifter, which is bigger but still cheap.

What Comes Next

You've now seen every operator that returns a single value. The next doc - Concatenation and Replication - covers the {} and {N{...}} syntax that builds wider vectors out of pieces, which you'll use constantly when interfacing between modules of different widths.