Verilog $display and $monitor: Printing From a Testbench

The C printf Family of Verilog

Three system tasks let you print to the simulator's stdout:

• $display - print once, append a newline.
• $write - print once, no newline.
• $monitor - print automatically every time a watched signal changes.

All three take a format string and a list of arguments, just like printf. The format specifiers are similar but Verilog-specific.

$display: The Default

$display is the workhorse:

module display_demo;
    reg [7:0] byte_val = 8'hAB;
    reg [3:0] nibble   = 4'b1010;
    integer   count    = 42;

    initial begin
        $display("Hello, world.");
        $display("byte_val  = %h", byte_val);
        $display("byte_val  = %b", byte_val);
        $display("byte_val  = %d", byte_val);
        $display("byte_val  = %0d (no padding)", byte_val);
        $display("multi: nibble=%b count=%0d", nibble, count);
        $finish;
    end
endmodule

You'll see something like:

Hello, world.
byte_val  = ab
byte_val  = 10101011
byte_val  = 171
byte_val  = 171 (no padding)
multi: nibble=1010 count=42

Notes:

• %d pads to a default width based on the operand size. For an 8-bit reg, that's 3 characters (room for 255). The leading spaces can look ugly in tabular output - use %0d to suppress them.
• %h, %b, %o have similar padding by default. Most testbench code uses %0 variants when the alignment isn't useful.
• The newline at the end is automatic. Don't put \n at the end of a $display format string - you'll get a blank line.

Format Specifiers

The set Verilog supports:

Specifier	Meaning
%b	binary
%d	decimal (signed if signal is signed)
%h or %x	hex
%o	octal
%c	single ASCII character (low 8 bits)
%s	string
%t	simulation time
%m	hierarchical name of the current scope
%%	a literal %
%0X	no leading padding, for any of %b, %d, etc.

%b, %d, %h, %o are the four you'll use 95% of the time. %t is the next most common - any time you want a timestamped log line.

$write: No Newline

$write is identical to $display except it doesn't append a newline:

module write_demo;
    initial begin
        $write("a");
        $write("b");
        $write("c");
        $display("");           // newline now
        $display("done");
        $finish;
    end
endmodule

Output:

abc
done

Useful for building a single line from a loop body:

$write("[");
for (integer i = 0; i < 8; i = i + 1) $write("%h ", arr[i]);
$display("]");

$monitor: Auto-Print on Change

$monitor registers a watch list. The simulator re-evaluates and prints whenever any signal mentioned in the format string changes:

module monitor_demo;
    reg [3:0] a, b;
    wire [4:0] sum;
    assign sum = a + b;

    initial begin
        $monitor("t=%0t a=%h b=%h sum=%h", $time, a, b, sum);

        a = 4'd1; b = 4'd2;     // first auto-print
        #5;
        a = 4'd5;                // second auto-print (a changed)
        #5;
        b = 4'd9;                // third auto-print (b changed)
        #5;
        $finish;
    end
endmodule

You'll see three lines, one for each change in the inputs. No need to manually call $display after every stimulus change - $monitor does it.

Two limitations:

• Only one $monitor can be active. Calling it again replaces the previous watch list. Use $monitoroff and $monitoron to temporarily suppress and re-enable.
• Changes within the same time step collapse to one print. If a and b both change at time 5, the monitor fires once with both new values, not twice.

When to Use Each

• $display: most testbench output. Call it explicitly after stimulus, after important state transitions, or inside a sampling always @(posedge clk) block.
• $write: when you want to build a single line from a loop or several small chunks.
• $monitor: when you want to track a small set of signals continuously and only see output when they change. Useful for initial debugging; harder to use in regression scripts because the output isn't deterministic in terms of total line count.

For most workflows, $display covers everything. Reach for $monitor only when continuous change-driven output is genuinely what you want.

Working With Time

$time returns the current simulation time as a 64-bit integer. Pair it with %0t:

$display("at %0t: signal flipped", $time);

The output looks like at 25: signal flipped (the unit depends on your timescale).

If you need sub-tick precision (rare), use $realtime instead - it returns a real.

%t automatically formats time with a default width that the simulator picks. %0t strips the padding.

Sampling on the Clock Edge

A clean idiom for monitoring sequential designs: a separate always @(posedge clk) block that prints once per cycle:

module sampler;
    reg clk = 0;
    reg [3:0] counter = 0;

    always #5 clk = ~clk;

    always @(posedge clk) begin
        counter <= counter + 1;
        $display("t=%0t cycle counter=%0d", $time, counter);
    end

    initial #100 $finish;
endmodule

This sampling pattern guarantees one log line per clock - perfect for regression tests that pattern-match on output.

Logging to a File

Open a file with $fopen, log with $fdisplay (which works like $display but writes to a file handle):

integer fd;
initial begin
    fd = $fopen("results.txt", "w");
    $fdisplay(fd, "test=%s status=%s", test_name, status);
    $fclose(fd);
end

$fopen returns a 32-bit handle; pass it as the first argument to $fdisplay, $fwrite, $fstrobe, and so on. The functions are otherwise identical to their console-printing siblings.

What Comes Next

$display and friends give you text logs. For visual debugging - watching signals as voltages over time - you want a VCD waveform. The next doc, Dumpfile and VCD, covers $dumpfile and $dumpvars, the two calls that turn your simulation into a graphical waveform you can scrub through.