Recap - Always vs Initial

Teil des Abschnitts Grundlagen der Verilog-Journey von Coddy. Lektion 51 von 90.

Aufgabe

always vs initial

Vervollständige beide block, damit dieser counter korrekt funktioniert.

Was zu tun ist:

Der initial-block sollte count zum Zeitpunkt 0 auf 0 initialisieren.
Der always-block sollte count bei jeder steigenden Taktflanke um 1 erhöhen.

Probier es selbst

module counter;
  reg clk;
  reg [3:0] count;
  
  // Taktgenerator (bereits gegeben)
  always #5 clk = ~clk;
  
  // TODO: Add initial block to set count = 0
  
  // TODO: Add always block to increment count on posedge clk
  
endmodule

Alle Lektionen in Grundlagen

1Einführung

Was ist Verilog Hardware vs. Software Ihr erstes Modul Kommentare Abstraktionsebenen des Designs

4Operators Part 1

Arithmetic Operators Modulo Operator Comparison Operators Recap - Simple Math Bitwise Operators

7Assign And Gates

Continuous Assignment Assign With Operators Built In Gate Primitives AND OR NOT Gates XOR XNOR Gates Recap - Logic Gate Circuit

10Decision Making

If Statement If - Else Recap - Simple Comparator Case Statement Casex And Casez Recap - ALU Design

13Timing And Delays

What Are Delays Gate Delays Assignment Delays Timescale Directive Clock Generation Recap - Timing Control

16Final Challenges

4 Bit Counter Decoder Design Shift Register

3Number System

Binary Representation Sized Numbers Unsized Numbers Negative Numbers Special Values X And Z Recap - Number Formats

6Modules

Module Structure Input And Output Ports Inout Ports Module Instantiation Port Mapping By Name Port Mapping By Order Recap - Build A Module

9Procedural Blocks

Always Block Initial Block Sensitivity List Blocking Assignment Non Blocking AssignmentRecap - Always vs Initial

12Multiplexer Project

2 To 1 Mux Design 4 To 1 Mux Design

Using Case Statement

15Traffic Light Controller

Defining The States State Machine Logic

Timing The Transitions

Writing The Testbench

Verifying The Output

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