Verifizieren des Outputs

module traffic_light (
  input clk,
  input reset,
  output reg red,
  output reg yellow,
  output reg green
);
  // Zustände: 0=Grün, 1=Gelb, 2=Rot
  reg [1:0] state;
  reg [5:0] counter;
  
  always @(posedge clk or posedge reset) begin
    if (reset) begin
      state <= 2;      // Starte bei Rot
      counter <= 0;
    end else begin
      if (counter == 0) begin
        // Zustand ändern
        if (state == 0) begin  // Grün -> Gelb
          state <= 1;
          counter <= 10;       // Gelb dauert 10 Sekunden
        end else if (state == 1) begin  // Gelb -> Rot
          state <= 2;
          counter <= 40;       // Rot dauert 40 Sekunden
        end else begin  // Rot -> Grün
          state <= 0;
          counter <= 30;       // Grün dauert 30 Sekunden
        end
      end else begin
        counter <= counter - 1;
      end
    end
  end
  
  // Ausgabelogik
  always @(*) begin
    red = (state == 2);
    yellow = (state == 1);
    green = (state == 0);
  end
  
endmodule

module testbench;
  reg clk, reset;
  wire red, yellow, green;
  
  traffic_light uut (
    .clk(clk),
    .reset(reset),
    .red(red),
    .yellow(yellow),
    .green(green)
  );
  
  always #1 clk = ~clk;
  
  initial begin
    // TODO: Füge $dumpfile hinzu, um "traffic.vcd" zu erstellen
    
    // TODO: Füge $dumpvars hinzu, um alle Signale zu dumpen (0, testbench)
    
    $display("Traffic Light Test");
    $monitor("Time %0t: red=%b, yellow=%b, green=%b", $time, red, yellow, green);
    
    clk = 0;
    reset = 1;
    #2 reset = 0;
    
    #90;
    $finish;
  end
endmodule