Accumulate Samples

Part of the RTL Design & Verification section of Coddy's Verilog journey. Lesson 31 of 38.

Build a reusable monitor for a stream of unsigned samples. You will accumulate values, honor enable and clear controls, count accepted samples and report whether a threshold is reached. All five steps keep the same module interface and locked testbench. Reserved outputs gain their behavior in later steps.

Challenge

Hard

Build one Sample Monitor over five steps. On each rising edge, synchronous rst clears total; otherwise add unsigned data to total. Use the 16-bit total register. At this first step en and clear are unused and the scenarios keep en=1 and clear=0. count and alarm are reserved outputs that stay zero. All input values are known. Scenarios contain at most 40 edges, so the total fits in 16 bits. The fixed testbench prints total for scenarios 1-9, total and count for scenarios 10-12, and total, count and alarm for scenarios 13-15. Only scenarios enabled for this step are graded.

Complete design.v and preserve its module names and ports. The locked testbench.v supplies input changes and prints the outputs after they settle. It chooses a scenario using a simulator argument such as +CASE=1; no standard input is required. Do not add printing, delays or simulation termination to the design. Expected output is one row of decimal values per observation, separated by one space and ending with a newline.

Try it yourself

module dut(input clk,rst,en,clear, input [7:0] data, input [15:0] limit, output reg [15:0] total, output reg [3:0] count, output alarm);
    initial begin total=0;count=0;end
    assign alarm=0;
endmodule