Recap - Dual Read Bank

Part of the RTL Design & Verification section of Coddy's Verilog journey. Lesson 25 of 38.

Challenge

Medium

Implement four 8-bit words with one clocked write and two registered old-data read outputs qa and qb. we writes at waddr. Synchronous rst clears only qa and qb. Otherwise re enables both reads from raddr_a and raddr_b; disabled reads hold. Same-edge writes do not change the old values captured by these reads. Tests initialize words before reading. Output columns: qa, qb. All controls and data are stable before each rising clock edge; results are observed afterward.

Complete design.v and preserve its module names and ports. The locked testbench.v supplies input changes and prints the outputs after they settle. It chooses a scenario using a simulator argument such as +CASE=1; no standard input is required. Do not add printing, delays or simulation termination to the design. Expected output is one row of decimal values per observation, separated by one space and ending with a newline.

Try it yourself

module dut (input clk, input rst, input we, input re, input [1:0] waddr, input [1:0] raddr_a, input [1:0] raddr_b, input [7:0] data, output reg [7:0] qa, output reg [7:0] qb);
    // Replace this placeholder with your design.
    initial qa = 0;
    initial qb = 0;
endmodule