Pipelining Data and Valid

Part of the RTL Design & Verification section of Coddy's Verilog journey. Lesson 18 of 38.

Pipelines separate work across registers. A valid flag travels beside each data item so a downstream stage can distinguish a sample from a bubble. With nonblocking assignments, a later stage reads the previous value of an earlier stage at the same edge. Reset should invalidate in-flight work.

Relevant excerpt; surrounding declarations and connections are supplied in the challenge.

always @(posedge clk) begin
    stage <= data;
    stage_valid <= in_valid;
    result <= stage;
    out_valid <= stage_valid;
end

Data and its validity move through the same number of registers.

Align data and valid through every pipeline stage and flush validity on reset.

Challenge

Medium

Implement a two-register-stage pipeline. On each non-reset edge, stage one captures a and in_valid. Stage two uses the previous stage-one values: out_valid becomes its old valid, and y becomes its old data plus one modulo 256 when valid, otherwise zero. Synchronous rst clears both stages and outputs. Output columns: y, out_valid. All controls and data are stable before each rising clock edge; results are observed afterward.

Complete design.v and preserve its module names and ports. The locked testbench.v supplies input changes and prints the outputs after they settle. It chooses a scenario using a simulator argument such as +CASE=1; no standard input is required. Do not add printing, delays or simulation termination to the design. Expected output is one row of decimal values per observation, separated by one space and ending with a newline.

Try it yourself

module dut (input clk, input rst, input in_valid, input [7:0] a, output reg [7:0] y, output reg out_valid);
    // Replace this placeholder with your design.
    initial y = 0;
    initial out_valid = 0;
endmodule