Read-Write Forwarding

Part of the RTL Design & Verification section of Coddy's Verilog journey. Lesson 24 of 38.

A memory interface must define same-address read/write behavior. Forwarding explicitly selects incoming write data for a collision, producing new-data behavior. Without that bypass, the previous nonblocking read template captures old data. Device memory modes differ, so simulation semantics alone do not guarantee a specific primitive mapping.

Relevant excerpt; surrounding declarations and connections are supplied in the challenge.

if(re) begin
    if(we && waddr==raddr) q <= data;
    else q <= mem[raddr];
end

The bypass selects the incoming word only for a real address collision.

Define collision behavior explicitly and verify it against the chosen hardware memory mode.

Challenge

Medium

Implement a registered-read four-word memory with new-data forwarding. The write and reset/read-enable rules match the prior lesson. On an enabled read colliding with an enabled write to the same address, q captures incoming data instead of the old word. For other reads it captures mem[raddr]. Output columns: q. All controls and data are stable before each rising clock edge; results are observed afterward.

Complete design.v and preserve its module names and ports. The locked testbench.v supplies input changes and prints the outputs after they settle. It chooses a scenario using a simulator argument such as +CASE=1; no standard input is required. Do not add printing, delays or simulation termination to the design. Expected output is one row of decimal values per observation, separated by one space and ending with a newline.

Try it yourself

module dut (input clk, input rst, input we, input re, input [1:0] waddr, input [1:0] raddr, input [7:0] data, output reg [7:0] q);
    // Replace this placeholder with your design.
    initial q = 0;
endmodule