Defaults Prevent Latches

Part of the RTL Design & Verification section of Coddy's Verilog journey. Lesson 1 of 38.

A combinational output must be assigned for every input path. If an always block skips assigning an output, that output retains its old value, which can infer a latch. A default assignment followed by overrides makes coverage visible.

Relevant excerpt; surrounding declarations and connections are supplied in the challenge.

always @* begin
    y = 0;
    if (en) y = data;
end

The default covers the disabled path, so the output depends only on current inputs.

Assign every combinational output on every path; use defaults before conditional overrides.

Challenge

Medium

Implement a gated 8-bit output: when en is one, y equals a; otherwise y is zero. Assign y on every combinational path. Output columns: y. All stimulus values are known binary values.

Complete design.v and preserve its module names and ports. The locked testbench.v supplies input changes and prints the outputs after they settle. It chooses a scenario using a simulator argument such as +CASE=1; no standard input is required. Do not add printing, delays or simulation termination to the design. Expected output is one row of decimal values per observation, separated by one space and ending with a newline.

Try it yourself

module dut (input en, input [7:0] a, output reg [7:0] y);
    // Replace this placeholder with your design.
    initial y = 0;
endmodule

Test yourself

This lesson includes a short quiz. Start the lesson to answer it and track your progress.

All lessons in RTL Design & Verification

1Reliable Combinational RTL

Defaults Prevent LatchesPriority Encoders One-Hot Validation Safe Case Decoding Recap - Request Router

4Controlled Sequential RTL

Reset and Enable Priority Saturating Counters Pipelining Data and Valid Detecting Sampled Edges Recap - Event Counter

7Project - Sample Monitor

Accumulate Samples Accept Enabled Samples

Clear the Current Window

Count Accepted Samples

Raise a Threshold Alarm

2Widths and Signed Arithmetic

Preserving Carry Bits Signed Comparisons Arithmetic Right Shifts Overflow and Saturation Recap - Signed Difference

5Memory and Lookup Tables

Combinational ROM Tables Register Array Storage Registered Read Ports Read-Write Forwarding Recap - Dual Read Bank

8Final Challenges

Challenge - Parity Pipeline Challenge - Pattern Events Challenge - Bounded Sum

3Reusable RTL

Combinational Functions Width-Safe Parameters Generate Loops Conditional Generate Recap - Reusable Bit Mask

6Self-Checking Testbenches

Four-State Checks Reusable Checker Tasks Reference Models and Scores Boundary and Control Coverage Recap - Adder Audit

Practice on your own: Online Verilog compiler