Challenge - Bounded Sum

Part of the RTL Design & Verification section of Coddy's Verilog journey. Lesson 38 of 38.

Challenge

Medium

Accumulate signed 8-bit sample into signed q on enabled rising edges, saturating at -128 and 127. Set sticky clipped whenever saturation occurs; once set, it remains set until rst or clear. Both synchronous controls clear q and clipped and have priority over en. Disabled edges hold both values. Output columns: q, clipped. All controls and data are stable before each rising clock edge; results are observed afterward.

Complete design.v and preserve its module names and ports. The locked testbench.v supplies input changes and prints the outputs after they settle. It chooses a scenario using a simulator argument such as +CASE=1; no standard input is required. Do not add printing, delays or simulation termination to the design. Expected output is one row of decimal values per observation, separated by one space and ending with a newline.

Try it yourself

module dut (input clk, input rst, input clear, input en, input signed [7:0] sample, output reg signed [7:0] q, output reg clipped);
    // Replace this placeholder with your design.
    initial q = 0;
    initial clipped = 0;
endmodule