Combinational ROM Tables

Part of the RTL Design & Verification section of Coddy's Verilog journey. Lesson 21 of 38.

A fixed lookup table describes a read-only mapping from address to data. A complete case or function can express the contents. With a combinational read, changing the address changes the output without waiting for a clock. The synthesis tool chooses an implementation; this source does not promise a particular FPGA memory primitive.

Relevant excerpt; surrounding declarations and connections are supplied in the challenge.

function [7:0] lookup;
    input [1:0] addr;
    begin
        case(addr)
            0: lookup=3;
            1: lookup=5;
            2: lookup=8;
            3: lookup=13;
            default: lookup=0;
        endcase
    end
endfunction

Every address selects a defined constant with no retained previous output.

Specify every table entry and distinguish combinational lookup from registered read latency.

Challenge

Medium

Implement a combinational eight-entry lookup table. Addresses 0 through 7 return 3,5,8,13,21,34,55,89 respectively. Use a complete case-based function to drive y. Output columns: y. All stimulus values are known binary values.

Complete design.v and preserve its module names and ports. The locked testbench.v supplies input changes and prints the outputs after they settle. It chooses a scenario using a simulator argument such as +CASE=1; no standard input is required. Do not add printing, delays or simulation termination to the design. Expected output is one row of decimal values per observation, separated by one space and ending with a newline.

Try it yourself

module dut (input [2:0] addr, output [7:0] y);
    // Replace this placeholder with your design.
    assign y = 0;
endmodule

Test yourself

This lesson includes a short quiz. Start the lesson to answer it and track your progress.

All lessons in RTL Design & Verification

1Reliable Combinational RTL

Defaults Prevent Latches Priority Encoders One-Hot Validation Safe Case Decoding Recap - Request Router

4Controlled Sequential RTL

Reset and Enable Priority Saturating Counters Pipelining Data and Valid Detecting Sampled Edges Recap - Event Counter

7Project - Sample Monitor

Accumulate Samples Accept Enabled Samples

Clear the Current Window

Count Accepted Samples

Raise a Threshold Alarm

2Widths and Signed Arithmetic

Preserving Carry Bits Signed Comparisons Arithmetic Right Shifts Overflow and Saturation Recap - Signed Difference

5Memory and Lookup Tables

Combinational ROM TablesRegister Array Storage Registered Read Ports Read-Write Forwarding Recap - Dual Read Bank

8Final Challenges

Challenge - Parity Pipeline Challenge - Pattern Events Challenge - Bounded Sum

3Reusable RTL

Combinational Functions Width-Safe Parameters Generate Loops Conditional Generate Recap - Reusable Bit Mask

6Self-Checking Testbenches

Four-State Checks Reusable Checker Tasks Reference Models and Scores Boundary and Control Coverage Recap - Adder Audit

Practice on your own: Online Verilog compiler