Reference Models and Scores

Part of the RTL Design & Verification section of Coddy's Verilog journey. Lesson 28 of 38.

A self-checking testbench computes expected behavior independently from the design output. A reference model can use straightforward arithmetic even when the implementation uses a different structure. A scoreboard counts observations and mismatches. Initialize its counters once per scenario and compare only after the design output has settled.

Relevant excerpt; surrounding declarations and connections are supplied in the challenge.

expected = {1'b0,a} + {1'b0,b};
checked = checked + 1;
if(actual !== expected) errors = errors + 1;

The expected value comes from the specified input behavior, not from copying actual.

Compute expected values independently, sample at a defined time and track every checked result.

Challenge

Medium

Implement a reference check for an unsigned four-bit adder. Compute the full five-bit mathematical a+b, then return ok=1 only if actual matches that result exactly in four-state comparison. This module contains a simulation-only task called by the locked testbench. Output columns: ok.

Complete design.v and preserve its module names and ports. The locked testbench.v supplies input changes and prints the outputs after they settle. It chooses a scenario using a simulator argument such as +CASE=1; no standard input is required. Keep printing and scenario control in the locked testbench; implement the task body only. Expected output is one row of decimal values per observation, separated by one space and ending with a newline.

Try it yourself

module dut;
    task check_sum;
        input [3:0] a,b;
        input [4:0] actual;
        output ok;
        reg [4:0] expected;
        begin
            // Complete the checker task.
            ok=0;
        end
    endtask
endmodule