Signed Comparisons

Part of the RTL Design & Verification section of Coddy's Verilog journey. Lesson 7 of 38.

The same bit pattern can represent different signed and unsigned numbers. Declare both operands signed when comparing two's-complement values. Mixing signed and unsigned operands can change the comparison interpretation. Concatenations are unsigned expressions, even when they contain signed signals.

Relevant excerpt; surrounding declarations and connections are supplied in the challenge.

wire signed [7:0] a,b;
assign less = a < b;

The signed declarations make negative values compare below nonnegative values.

Keep comparison operands consistently signed and extend signed values with their sign bit.

Challenge

Medium

Compare signed 8-bit a and b. Output less when a is less than b, and equal when they are equal. Both inputs are two's-complement signed values. Output columns: less, equal. All stimulus values are known binary values.

Complete design.v and preserve its module names and ports. The locked testbench.v supplies input changes and prints the outputs after they settle. It chooses a scenario using a simulator argument such as +CASE=1; no standard input is required. Do not add printing, delays or simulation termination to the design. Expected output is one row of decimal values per observation, separated by one space and ending with a newline.

Try it yourself

module dut (input signed [7:0] a, input signed [7:0] b, output less, output equal);
    // Replace this placeholder with your design.
    assign less = 0;
    assign equal = 0;
endmodule