Priority Encoders

Part of the RTL Design & Verification section of Coddy's Verilog journey. Lesson 2 of 38.

An encoder maps a request bit to an index. Multiple active requests need an explicit priority rule. An if/else-if chain gives earlier branches priority; a separate valid signal distinguishes no request from index zero.

Relevant excerpt; surrounding declarations and connections are supplied in the challenge.

if (req[3]) code = 3;
else if (req[2]) code = 2;
else if (req[1]) code = 1;
else code = 0;

The first true branch wins, giving the highest request bit priority.

State the priority order and define the no-request output explicitly.

Challenge

Medium

Encode the highest asserted bit of 4-bit req into code. Set valid if any request exists; when req is zero, code and valid are zero. Output columns: code, valid. All stimulus values are known binary values.

Complete design.v and preserve its module names and ports. The locked testbench.v supplies input changes and prints the outputs after they settle. It chooses a scenario using a simulator argument such as +CASE=1; no standard input is required. Do not add printing, delays or simulation termination to the design. Expected output is one row of decimal values per observation, separated by one space and ending with a newline.

Try it yourself

module dut (input [3:0] req, output reg [1:0] code, output reg valid);
    // Replace this placeholder with your design.
    initial code = 0;
    initial valid = 0;
endmodule