Recap - Request Router

Part of the RTL Design & Verification section of Coddy's Verilog journey. Lesson 5 of 38.

Challenge

Medium

Accept a 4-bit request only if exactly one bit is set. When valid, output the selected bit index in code and set valid. For idle or multiple requests, both code and valid are zero. Output columns: code, valid. All stimulus values are known binary values.

Complete design.v and preserve its module names and ports. The locked testbench.v supplies input changes and prints the outputs after they settle. It chooses a scenario using a simulator argument such as +CASE=1; no standard input is required. Do not add printing, delays or simulation termination to the design. Expected output is one row of decimal values per observation, separated by one space and ending with a newline.

Try it yourself

module dut (input [3:0] req, output reg [1:0] code, output reg valid);
    // Replace this placeholder with your design.
    initial code = 0;
    initial valid = 0;
endmodule