Arithmetic Right Shifts

Part of the RTL Design & Verification section of Coddy's Verilog journey. Lesson 8 of 38.

An arithmetic right shift uses >>> and replicates the sign bit when its left operand is signed. A logical right shift uses >> and fills with zeros. For a negative odd value, arithmetic shifting right is not the same as integer division that truncates toward zero.

Relevant excerpt; surrounding declarations and connections are supplied in the challenge.

reg signed [7:0] value;
value = -3;
$display("%0d", value >>> 1);

The result is minus two because sign extension retains the negative two's-complement interpretation.

Use a signed left operand with >>> when sign extension is required.

Challenge

Medium

Arithmetic-right-shift signed 8-bit value by amount (0 to 7). Return the signed 8-bit result y. Negative values fill with their sign bit. Output columns: y. All stimulus values are known binary values.

Complete design.v and preserve its module names and ports. The locked testbench.v supplies input changes and prints the outputs after they settle. It chooses a scenario using a simulator argument such as +CASE=1; no standard input is required. Do not add printing, delays or simulation termination to the design. Expected output is one row of decimal values per observation, separated by one space and ending with a newline.

Try it yourself

module dut (input signed [7:0] value, input [2:0] amount, output signed [7:0] y);
    // Replace this placeholder with your design.
    assign y = 0;
endmodule