Recap - Signed Difference

Part of the RTL Design & Verification section of Coddy's Verilog journey. Lesson 10 of 38.

Challenge

Medium

Compute signed 8-bit a minus b with saturation to -128 through 127. Return saturated y and clipped=1 when the exact difference is outside that range. Output columns: y, clipped. All stimulus values are known binary values.

Complete design.v and preserve its module names and ports. The locked testbench.v supplies input changes and prints the outputs after they settle. It chooses a scenario using a simulator argument such as +CASE=1; no standard input is required. Do not add printing, delays or simulation termination to the design. Expected output is one row of decimal values per observation, separated by one space and ending with a newline.

Try it yourself

module dut (input signed [7:0] a, input signed [7:0] b, output reg signed [7:0] y, output reg clipped);
    // Replace this placeholder with your design.
    initial y = 0;
    initial clipped = 0;
endmodule