Challenge - Pattern Events

Part of the RTL Design & Verification section of Coddy's Verilog journey. Lesson 37 of 38.

Challenge

Medium

Detect the bit pattern 101 in accepted input samples. en=1 accepts bit_in on the rising edge; en=0 preserves partial-match state and produces hit=0. Set registered hit=1 only on an accepted bit completing 101. Overlapping matches are allowed: 10101 produces two pulses. Synchronous rst clears state and hit, taking priority over en. Output columns: hit. All controls and data are stable before each rising clock edge; results are observed afterward.

Complete design.v and preserve its module names and ports. The locked testbench.v supplies input changes and prints the outputs after they settle. It chooses a scenario using a simulator argument such as +CASE=1; no standard input is required. Do not add printing, delays or simulation termination to the design. Expected output is one row of decimal values per observation, separated by one space and ending with a newline.

Try it yourself

module dut (input clk, input rst, input en, input bit_in, output reg hit);
    // Replace this placeholder with your design.
    initial hit = 0;
endmodule