Conditional Generate

Part of the RTL Design & Verification section of Coddy's Verilog journey. Lesson 14 of 38.

A generate-if selects a hardware structure using a constant parameter. Only one branch is elaborated for a given instance. A procedural if or conditional expression with a signal selects behavior at runtime; it does not replace generate configuration.

Relevant excerpt; surrounding declarations and connections are supplied in the challenge.

generate
    if(INVERT) begin: inverted
        assign y = ~a;
    end else begin: direct
        assign y = a;
    end
endgenerate

The parameter chooses which driver is constructed for this instance.

Use generate-if for constant configuration and ordinary RTL selection for runtime controls.

Challenge

Medium

Use conditional generate: MODE=0 passes a unchanged; MODE=1 inverts all eight bits of a. Input b is unused. MODE is either 0 or 1. The testbench instantiates both configurations and prints y0 then y1.

Complete design.v and preserve its module names and ports. The locked testbench.v supplies input changes and prints the outputs after they settle. It chooses a scenario using a simulator argument such as +CASE=1; no standard input is required. Do not add printing, delays or simulation termination to the design. Expected output is one row of decimal values per observation, separated by one space and ending with a newline.

Try it yourself

module dut #(parameter MODE=0) (input [7:0] a,b, output [7:0] y);
    assign y=0;
endmodule

Test yourself

This lesson includes a short quiz. Start the lesson to answer it and track your progress.

All lessons in RTL Design & Verification

1Reliable Combinational RTL

Defaults Prevent Latches Priority Encoders One-Hot Validation Safe Case Decoding Recap - Request Router

4Controlled Sequential RTL

Reset and Enable Priority Saturating Counters Pipelining Data and Valid Detecting Sampled Edges Recap - Event Counter

7Project - Sample Monitor

Accumulate Samples Accept Enabled Samples

Clear the Current Window

Count Accepted Samples

Raise a Threshold Alarm

2Widths and Signed Arithmetic

Preserving Carry Bits Signed Comparisons Arithmetic Right Shifts Overflow and Saturation Recap - Signed Difference

5Memory and Lookup Tables

Combinational ROM Tables Register Array Storage Registered Read Ports Read-Write Forwarding Recap - Dual Read Bank

8Final Challenges

Challenge - Parity Pipeline Challenge - Pattern Events Challenge - Bounded Sum

3Reusable RTL

Combinational Functions Width-Safe Parameters Generate LoopsConditional GenerateRecap - Reusable Bit Mask

6Self-Checking Testbenches

Four-State Checks Reusable Checker Tasks Reference Models and Scores Boundary and Control Coverage Recap - Adder Audit

Practice on your own: Online Verilog compiler