Detecting Sampled Edges

Part of the RTL Design & Verification section of Coddy's Verilog journey. Lesson 19 of 38.

A level can remain high for many cycles, while an event pulse should last for one cycle. Store the previous sampled level and compare it with the current one. This edge detector assumes an input already synchronous to this clock; it is not a clock-domain crossing synchronizer.

Relevant excerpt; surrounding declarations and connections are supplied in the challenge.

previous <= sig;
rising <= sig & ~previous;

The old stored level makes a single pulse at the sampled transition.

Compare current and previous sampled levels; use this detector only with a synchronous input.

Challenge

Medium

For a signal sig already synchronous to clk, produce a registered one-cycle pulse on each sampled 0-to-1 transition. Synchronous rst clears the stored previous level and pulse. A high sig on the first non-reset edge therefore produces a pulse. Output columns: pulse. All controls and data are stable before each rising clock edge; results are observed afterward.

Complete design.v and preserve its module names and ports. The locked testbench.v supplies input changes and prints the outputs after they settle. It chooses a scenario using a simulator argument such as +CASE=1; no standard input is required. Do not add printing, delays or simulation termination to the design. Expected output is one row of decimal values per observation, separated by one space and ending with a newline.

Try it yourself

module dut (input clk, input rst, input sig, output reg pulse);
    // Replace this placeholder with your design.
    initial pulse = 0;
endmodule

Test yourself

This lesson includes a short quiz. Start the lesson to answer it and track your progress.

All lessons in RTL Design & Verification

1Reliable Combinational RTL

Defaults Prevent Latches Priority Encoders One-Hot Validation Safe Case Decoding Recap - Request Router

4Controlled Sequential RTL

Reset and Enable Priority Saturating Counters Pipelining Data and ValidDetecting Sampled EdgesRecap - Event Counter

7Project - Sample Monitor

Accumulate Samples Accept Enabled Samples

Clear the Current Window

Count Accepted Samples

Raise a Threshold Alarm

2Widths and Signed Arithmetic

Preserving Carry Bits Signed Comparisons Arithmetic Right Shifts Overflow and Saturation Recap - Signed Difference

5Memory and Lookup Tables

Combinational ROM Tables Register Array Storage Registered Read Ports Read-Write Forwarding Recap - Dual Read Bank

8Final Challenges

Challenge - Parity Pipeline Challenge - Pattern Events Challenge - Bounded Sum

3Reusable RTL

Combinational Functions Width-Safe Parameters Generate Loops Conditional Generate Recap - Reusable Bit Mask

6Self-Checking Testbenches

Four-State Checks Reusable Checker Tasks Reference Models and Scores Boundary and Control Coverage Recap - Adder Audit

Practice on your own: Online Verilog compiler