Recap - Reusable Bit Mask

Part of the RTL Design & Verification section of Coddy's Verilog journey. Lesson 15 of 38.

Challenge

Medium

Build a WIDTH-bit bit-clear circuit with a named generate loop: each output bit equals the corresponding a bit AND the inverse of b at that position. b is a clear mask. WIDTH is positive. The locked testbench instantiates WIDTH values 1, 4 and 8, using the low bits of a and b for narrower instances. Output columns are y1, y4 and y8 in decimal.

Complete design.v and preserve its module names and ports. The locked testbench.v supplies input changes and prints the outputs after they settle. It chooses a scenario using a simulator argument such as +CASE=1; no standard input is required. Do not add printing, delays or simulation termination to the design. Expected output is one row of decimal values per observation, separated by one space and ending with a newline.

Try it yourself

module dut #(parameter WIDTH=4) (input [WIDTH-1:0] a,b, output [WIDTH-1:0] y);
    // Implement the parameterized circuit.
    assign y = 0;
endmodule