Combinational Functions

Part of the RTL Design & Verification section of Coddy's Verilog journey. Lesson 11 of 38.

A Verilog function packages a zero-time calculation for reuse within a module. Declare its return width, input arguments and local variables, then assign the result to the function name. Combinational functions contain no delays or event controls; a loop with fixed bounds can describe repeated logic.

Relevant excerpt; surrounding declarations and connections are supplied in the challenge.

function [7:0] gray;
    input [7:0] value;
    begin gray = value ^ (value >> 1); end
endfunction

Calling the function computes an expression without adding simulation time.

Assign the function result on every path and keep combinational functions free of timing controls.

Challenge

Medium

Implement a Verilog function gray that converts an unsigned 8-bit binary value to Gray code using value XOR (value shifted right by one). Drive y by calling the function with a. Output columns: y. All stimulus values are known binary values.

Complete design.v and preserve its module names and ports. The locked testbench.v supplies input changes and prints the outputs after they settle. It chooses a scenario using a simulator argument such as +CASE=1; no standard input is required. Do not add printing, delays or simulation termination to the design. Expected output is one row of decimal values per observation, separated by one space and ending with a newline.

Try it yourself

module dut (input [7:0] a, output [7:0] y);
    // Replace this placeholder with your design.
    assign y = 0;
endmodule

Test yourself

This lesson includes a short quiz. Start the lesson to answer it and track your progress.

All lessons in RTL Design & Verification

1Reliable Combinational RTL

Defaults Prevent Latches Priority Encoders One-Hot Validation Safe Case Decoding Recap - Request Router

4Controlled Sequential RTL

Reset and Enable Priority Saturating Counters Pipelining Data and Valid Detecting Sampled Edges Recap - Event Counter

7Project - Sample Monitor

Accumulate Samples Accept Enabled Samples

Clear the Current Window

Count Accepted Samples

Raise a Threshold Alarm

2Widths and Signed Arithmetic

Preserving Carry Bits Signed Comparisons Arithmetic Right Shifts Overflow and Saturation Recap - Signed Difference

5Memory and Lookup Tables

Combinational ROM Tables Register Array Storage Registered Read Ports Read-Write Forwarding Recap - Dual Read Bank

8Final Challenges

Challenge - Parity Pipeline Challenge - Pattern Events Challenge - Bounded Sum

3Reusable RTL

Combinational FunctionsWidth-Safe Parameters Generate Loops Conditional Generate Recap - Reusable Bit Mask

6Self-Checking Testbenches

Four-State Checks Reusable Checker Tasks Reference Models and Scores Boundary and Control Coverage Recap - Adder Audit

Practice on your own: Online Verilog compiler