Overflow and Saturation

Part of the RTL Design & Verification section of Coddy's Verilog journey. Lesson 9 of 38.

Signed overflow means the mathematical result cannot fit in the chosen signed width. It differs from unsigned carry. For signed addition, equal-sign inputs overflow when the result sign changes. Saturation clamps to a representable endpoint instead of wrapping.

Relevant excerpt; surrounding declarations and connections are supplied in the challenge.

assign overflow = (a[7] == b[7]) && (sum[7] != a[7]);

Different-sign inputs cannot overflow signed addition; equal-sign inputs require a result-sign check.

Check signed overflow independently of carry; widen before implementing saturation.

Challenge

Medium

Add signed 8-bit a and b. Return the wrapped signed result y and overflow=1 only when the exact mathematical sum is outside -128 through 127. Output columns: y, overflow. All stimulus values are known binary values.

Complete design.v and preserve its module names and ports. The locked testbench.v supplies input changes and prints the outputs after they settle. It chooses a scenario using a simulator argument such as +CASE=1; no standard input is required. Do not add printing, delays or simulation termination to the design. Expected output is one row of decimal values per observation, separated by one space and ending with a newline.

Try it yourself

module dut (input signed [7:0] a, input signed [7:0] b, output signed [7:0] y, output overflow);
    // Replace this placeholder with your design.
    assign y = 0;
    assign overflow = 0;
endmodule