Recap - Event Counter

Part of the RTL Design & Verification section of Coddy's Verilog journey. Lesson 20 of 38.

Challenge

Medium

Count sampled rising transitions of synchronous sig in 4-bit count. Saturate at 15. Synchronous rst clears count and previous level. High sig immediately after reset counts as a rising event. Output columns: count. All controls and data are stable before each rising clock edge; results are observed afterward.

Complete design.v and preserve its module names and ports. The locked testbench.v supplies input changes and prints the outputs after they settle. It chooses a scenario using a simulator argument such as +CASE=1; no standard input is required. Do not add printing, delays or simulation termination to the design. Expected output is one row of decimal values per observation, separated by one space and ending with a newline.

Try it yourself

module dut (input clk, input rst, input sig, output reg [3:0] count);
    // Replace this placeholder with your design.
    initial count = 0;
endmodule