Reusable Checker Tasks

Part of the RTL Design & Verification section of Coddy's Verilog journey. Lesson 27 of 38.

A Verilog task groups procedural work and can return results through output or inout arguments. Testbench tasks reduce duplicated checks. Unlike a combinational function, a task can include timing controls when appropriate, but these checker tasks perform only zero-time comparisons. Use automatic tasks if separate concurrent calls need independent local storage; the supplied calls here are sequential.

Relevant excerpt; surrounding declarations and connections are supplied in the challenge.

task check_value;
    input [7:0] actual,expected;
    output ok;
    begin ok = (actual === expected); end
endtask

The caller receives the check result through an explicit output argument.

Define task argument directions and reset per-call result variables before collecting failures.

Challenge

Medium

Implement check_value so ok is one when actual and expected match under four-state equality and zero otherwise. This module contains a simulation-only task called by the locked testbench. Output columns: ok.

Complete design.v and preserve its module names and ports. The locked testbench.v supplies input changes and prints the outputs after they settle. It chooses a scenario using a simulator argument such as +CASE=1; no standard input is required. Keep printing and scenario control in the locked testbench; implement the task body only. Expected output is one row of decimal values per observation, separated by one space and ending with a newline.

Try it yourself

module dut;
    task check_value;
        input [7:0] actual,expected;
        output ok;
        begin
            // Complete the checker task.
            ok=0;
        end
    endtask
endmodule