Recap - Adder Audit

Part of the RTL Design & Verification section of Coddy's Verilog journey. Lesson 30 of 38.

Challenge

Medium

Implement audit for a four-bit unsigned adder. Accumulate checked and errors as in the scoreboard lesson, and preserve coverage bits: bit 0 marks a=b=0, bit 1 marks a=b=15, and bit 2 marks every other input pair. Compare actual against the full five-bit sum using four-state inequality. The caller initializes all counters and flags. This module contains a simulation-only task called by the locked testbench. Output columns: checked, errors, seen.

Complete design.v and preserve its module names and ports. The locked testbench.v supplies input changes and prints the outputs after they settle. It chooses a scenario using a simulator argument such as +CASE=1; no standard input is required. Keep printing and scenario control in the locked testbench; implement the task body only. Expected output is one row of decimal values per observation, separated by one space and ending with a newline.

Try it yourself

module dut;
    task audit;
        input [3:0] a,b;
        input [4:0] actual;
        inout integer checked,errors;
        inout [2:0] seen;
        reg [4:0] expected;
        begin
            // Complete the checker task.
            checked=checked;errors=errors;seen=seen;
        end
    endtask
endmodule