Challenge - Parity Pipeline

Part of the RTL Design & Verification section of Coddy's Verilog journey. Lesson 36 of 38.

Challenge

Medium

Build a two-stage parity pipeline. First capture byte data and in_valid. On the following non-reset edge, output parity is the reduction XOR of the previous captured byte when its previous valid is high, otherwise zero. out_valid is that delayed valid. Synchronous rst clears both stages and outputs. Output columns: parity, out_valid. All controls and data are stable before each rising clock edge; results are observed afterward.

Complete design.v and preserve its module names and ports. The locked testbench.v supplies input changes and prints the outputs after they settle. It chooses a scenario using a simulator argument such as +CASE=1; no standard input is required. Do not add printing, delays or simulation termination to the design. Expected output is one row of decimal values per observation, separated by one space and ending with a newline.

Try it yourself

module dut (input clk, input rst, input in_valid, input [7:0] data, output reg parity, output reg out_valid);
    // Replace this placeholder with your design.
    initial parity = 0;
    initial out_valid = 0;
endmodule