Four-State Checks

Part of the RTL Design & Verification section of Coddy's Verilog journey. Lesson 26 of 38.

A testbench must treat unknowns deliberately. Ordinary equality may return X, which can hide a failure in an if condition. Case equality and inequality, === and !==, compare all four values literally and return a known Boolean. Reduction XOR followed by case comparison with X can detect unknown bits. Use these as simulation checks, not as a model of hardware that detects physical X values.

Relevant excerpt; surrounding declarations and connections are supplied in the challenge.

if(actual !== expected) errors = errors + 1;

A difference involving X or Z is counted instead of disappearing into an unknown condition.

Use explicit four-state comparisons in simulation checkers and define how unknowns should be treated.

Challenge

Medium

This is a simulation-only checker, not synthesizable datapath logic. Set mismatch when actual and expected differ under four-state comparison. If both have the same X or Z in the same positions, they compare equal. The result must always be a known 0 or 1. Output columns: mismatch. All stimulus values are known binary values.

Complete design.v and preserve its module names and ports. The locked testbench.v supplies input changes and prints the outputs after they settle. It chooses a scenario using a simulator argument such as +CASE=1; no standard input is required. Do not add printing, delays or simulation termination to the design. Expected output is one row of decimal values per observation, separated by one space and ending with a newline.

Try it yourself

module dut (input [3:0] actual, input [3:0] expected, output mismatch);
    // Replace this placeholder with your design.
    assign mismatch = 0;
endmodule