Reset and Enable Priority

Part of the RTL Design & Verification section of Coddy's Verilog journey. Lesson 16 of 38.

A clocked block can hold a register by omitting an assignment on disabled edges. This intentional storage differs from an accidental combinational latch. Write an explicit priority among reset, load and enable. Here resets are synchronous: they take effect only at the rising clock edge.

Relevant excerpt; surrounding declarations and connections are supplied in the challenge.

always @(posedge clk) begin
    if(rst) q <= 0;
    else if(en) q <= data;
end

Reset wins when both controls are asserted, and disabled non-reset edges retain q.

Use one clocked priority chain and define reset, load, enable and hold behavior precisely.

Challenge

Medium

Implement an 8-bit register q with active-high synchronous reset rst and enable en. On a rising edge, reset wins and clears q; otherwise enabled edges load a; disabled edges hold q. Output columns: q. All controls and data are stable before each rising clock edge; results are observed afterward.

Complete design.v and preserve its module names and ports. The locked testbench.v supplies input changes and prints the outputs after they settle. It chooses a scenario using a simulator argument such as +CASE=1; no standard input is required. Do not add printing, delays or simulation termination to the design. Expected output is one row of decimal values per observation, separated by one space and ending with a newline.

Try it yourself

module dut (input clk, input rst, input en, input [7:0] a, output reg [7:0] q);
    // Replace this placeholder with your design.
    initial q = 0;
endmodule