Saturating Counters

Part of the RTL Design & Verification section of Coddy's Verilog journey. Lesson 17 of 38.

Fundamentals used a wrapping counter. A saturating counter instead stops at a boundary, which is useful for bounded counts. Add an explicit guard to the arithmetic update and keep enable and reset behavior independent of the limit.

Relevant excerpt; surrounding declarations and connections are supplied in the challenge.

always @(posedge clk) begin
    if(rst) count <= 0;
    else if(en && count != 15) count <= count + 1;
end

The maximum value is retained rather than wrapping to zero.

Guard boundary updates explicitly when a counter must saturate instead of wrap.

Challenge

Medium

Create a 4-bit saturating counter q. Synchronous rst clears it. Enabled edges increment until 15, then hold at 15; disabled edges also hold. Reset has priority. Output columns: q. All controls and data are stable before each rising clock edge; results are observed afterward.

Complete design.v and preserve its module names and ports. The locked testbench.v supplies input changes and prints the outputs after they settle. It chooses a scenario using a simulator argument such as +CASE=1; no standard input is required. Do not add printing, delays or simulation termination to the design. Expected output is one row of decimal values per observation, separated by one space and ending with a newline.

Try it yourself

module dut (input clk, input rst, input en, output reg [3:0] q);
    // Replace this placeholder with your design.
    initial q = 0;
endmodule

Test yourself

This lesson includes a short quiz. Start the lesson to answer it and track your progress.

All lessons in RTL Design & Verification

1Reliable Combinational RTL

Defaults Prevent Latches Priority Encoders One-Hot Validation Safe Case Decoding Recap - Request Router

4Controlled Sequential RTL

Reset and Enable PrioritySaturating CountersPipelining Data and Valid Detecting Sampled Edges Recap - Event Counter

7Project - Sample Monitor

Accumulate Samples Accept Enabled Samples

Clear the Current Window

Count Accepted Samples

Raise a Threshold Alarm

2Widths and Signed Arithmetic

Preserving Carry Bits Signed Comparisons Arithmetic Right Shifts Overflow and Saturation Recap - Signed Difference

5Memory and Lookup Tables

Combinational ROM Tables Register Array Storage Registered Read Ports Read-Write Forwarding Recap - Dual Read Bank

8Final Challenges

Challenge - Parity Pipeline Challenge - Pattern Events Challenge - Bounded Sum

3Reusable RTL

Combinational Functions Width-Safe Parameters Generate Loops Conditional Generate Recap - Reusable Bit Mask

6Self-Checking Testbenches

Four-State Checks Reusable Checker Tasks Reference Models and Scores Boundary and Control Coverage Recap - Adder Audit

Practice on your own: Online Verilog compiler