Clear the Current Window

Part of the RTL Design & Verification section of Coddy's Verilog journey. Lesson 33 of 38.

Challenge

Hard

Build one Sample Monitor over five steps. Add synchronous clear with priority after rst and before en. clear resets total without accepting data on that edge, even when en=1. Keep the reset and enable behavior. Keep everything from the previous steps, including its testbench and earlier output behavior. All input values are known. Scenarios contain at most 40 edges, so the total fits in 16 bits. The fixed testbench prints total for scenarios 1-9, total and count for scenarios 10-12, and total, count and alarm for scenarios 13-15. Only scenarios enabled for this step are graded.

Complete design.v and preserve its module names and ports. The locked testbench.v supplies input changes and prints the outputs after they settle. It chooses a scenario using a simulator argument such as +CASE=1; no standard input is required. Do not add printing, delays or simulation termination to the design. Expected output is one row of decimal values per observation, separated by one space and ending with a newline.

Try it yourself

module dut(input clk,rst,en,clear, input [7:0] data, input [15:0] limit, output reg [15:0] total, output reg [3:0] count, output alarm);
    always @(posedge clk)begin
        if(rst)total<=0;else if(en)total<=total+data;
        count<=0;
    end
    assign alarm=0;
endmodule