2 To 1 Mux Design

Part of the Fundamentals section of Coddy's Verilog journey — lesson 64 of 90.

Challenge

A multiplexer (MUX) is a digital circuit that selects one of several inputs and forwards it to a single output based on a select signal. Think of it like a data selector — you have multiple inputs coming in, and you choose which one goes to the output.

In this project, you will build multiplexers of different sizes using if-else and case statements.

2-to-1 Multiplexer

The 2-to-1 multiplexer is the simplest form. It has two data inputs (in0 and in1), one select input (sel), and one output (out). When sel is 0, the output follows in0. When sel is 1, the output follows in1. You will implement this using an if-else statement inside an always @(*) block.

Example: If in0 = 0, in1 = 1, and sel = 1, then out = 1.

A 2-to-1 multiplexer selects one of two inputs and passes it to the output based on a select signal.

Truth Table

sel	out
0	out = in0
1	out = in1

When sel is 0, the output follows in0. When sel is 1, the output follows in1.

What to do:

Create a module named mux2to1
Add input in0 (1 bit)
Add input in1 (1 bit)
Add input sel (1 bit)
Add output out (1 bit, type reg)
Add an always @(*) block
Inside, add an if-else statement:
- If sel == 0, set out = in0
- Else, set out = in1
Close with endmodule

Try it yourself

// Step 1: Create module named mux2to1


  // Step 2: Add input in0
  
  // Step 3: Add input in1
  
  // Step 4: Add input sel
  
  // Step 5: Add output out (reg type)
  

  // Step 6: Add always @(*) block
  

    // Step 7: Add if-else statement
    // If sel == 0, out = in0
    // Else, out = in1
    

// Step 8: Endmodule