Forever Loop

Part of the Fundamentals section of Coddy's Verilog journey — lesson 61 of 90.

The forever loop repeats a block of code continuously, forever. It never stops on its own.

A forever loop executes repeatedly without end. It is useful for generating clocks and other continuous signals in testbenches.

Syntax:

forever begin
  // Code that repeats forever
end

Simple Example

forever begin
  $display("This prints forever");
end

This will print endlessly and crash your simulation. Always add a delay or a stopping condition.

Generating a Clock (Common Use)

The most common use of forever is to generate a clock:

initial begin
  clk = 0;
  forever begin
    #5 clk = ~clk;   // Toggle every 5 time units
  end
end

This creates a clock that runs for the entire simulation.

Forever with Disable

You can stop a forever loop using a disable statement:

initial begin : clock_gen   // Name added here
  clk = 0;
  forever begin
    #5 clk = ~clk;
  end
end

initial begin
  #100;
  disable clock_gen;   // Now this works
end

Forever vs Other Loops

Loop	Stops?	When to Use
`for`	Yes (after fixed iterations)	Known number of repeats
`while`	Yes (when condition false)	Unknown stop condition
`repeat`	Yes (after fixed iterations)	Known number of repeats
`forever`	No (never)	Continuous signals (clock)

Important Rules

Rule	Explanation
Must include a delay	`#10` or `@(posedge clk)`
Without delay, simulation hangs	Infinite loop with no time advance
Use with `disable` to stop	Or simulation never ends
Best used in testbenches	Not synthesizable

Challenge

What to do:

Add the missing forever loop to generate a clock that toggles every 10 time units.

Cheat sheet

The forever loop repeats a block of code continuously without stopping. Always include a delay to prevent simulation hang.

initial begin
  clk = 0;
  forever begin
    #5 clk = ~clk; // Toggle every 5 time units
  end
end

Stop a forever loop using disable with a named block:

initial begin : clock_gen
  clk = 0;
  forever begin
    #5 clk = ~clk;
  end
end

initial begin
  #100;
  disable clock_gen;
end

Key rules:

Must include a delay (#10 or @(posedge clk)), otherwise simulation hangs
Use disable to stop, or simulation never ends
Not synthesizable — testbench use only

Try it yourself

module forever_challenge;
  reg clk;
  
  initial begin
    clk = 0;
    // TODO: Add forever loop to toggle clk every 10 time units
  end
endmodule

Test yourself

This lesson includes a short quiz. Start the lesson to answer it and track your progress.

All lessons in Fundamentals

1Introduction

What Is Verilog Hardware vs Software Design Abstraction Levels Your First Module Comments

4Operators Part 1

Arithmetic Operators Modulo Operator Comparison Operators Recap - Simple Math Bitwise Operators

7Assign And Gates

Continuous Assignment Assign With Operators Built In Gate Primitives AND OR NOT Gates XOR XNOR Gates Recap - Logic Gate Circuit

10Decision Making

If Statement If - Else Recap - Simple Comparator Case Statement Casex And Casez Recap - ALU Design

13Timing And Delays

What Are Delays Gate Delays Assignment Delays Timescale Directive Clock Generation Recap - Timing Control

16Final Challenges

4 Bit Counter Decoder Design Shift Register

2Data Types

Wire Type Reg Type Integer And Real Vectors Arrays Parameters Recap - Declare Signals

5Operators Part 2

Logical Operators Reduction Operators Shift Operators Concatenation Operator Conditional Operator Recap - Operator Challenge

8Half Adder Project

Writing The Module Designing The Logic

Writing The Testbench

11Loops

For Loop While Loop Repeat LoopForever LoopDisable Statement Recap - Loop Patterns

14Testbench Basics

What Is A Testbench Creating Stimulus Display And Monitor Dumpfile And Dumpvars Using System Tasks Recap - Full Testbench

17UART

Bit counter State Machine

Transmitter Design

Testbench