Dumpfile And Dumpvars

Part of the Fundamentals section of Coddy's Verilog journey — lesson 76 of 90.

Waveforms are the visual representation of signal changes over time. A waveform displays how signals (like clk, a, b, out) change during simulation. The horizontal axis shows time, and the vertical axis shows signal values (0, 1, X, Z).

$dumpfile and $dumpvars are system tasks used to create a waveform file (VCD file) that you can view in a waveform viewer like GTKWave. VCD stands for Value Change Dump. It is a file that records all signal changes during simulation. You can open this file in a waveform viewer to see signals visually.

$dumpfile

$dumpfile specifies the name of the waveform file to create.

Syntax:

$dumpfile("filename.vcd");

Example:

$dumpfile("my_waveform.vcd");

This creates a file called my_waveform.vcd.

$dumpvars

$dumpvars specifies which signals to record in the waveform file.

Syntax:

$dumpvars(level, module_name);

Parameter	Meaning
`level`	How many hierarchy levels to dump (0 = all levels)
`module_name`	Which module to dump signals from

Note: Hierarchy means modules inside other modules. Using 0 dumps all signals from the top module and every module inside it, while 1 dumps only signals from the top module.

Common Usage

initial begin
  $dumpfile("dump.vcd");
  $dumpvars(0, testbench);
end

$dumpfile("dump.vcd") → creates file named dump.vcd
$dumpvars(0, testbench) → dumps all signals in module testbench and all sub-modules

Example with Testbench

module or_gate (
  input x,
  input y,
  output z
);
  assign z = x | y;
endmodule

module testbench;
  reg x, y;
  wire z;
  
  or_gate dut (
    .x(x),
    .y(y),
    .z(z)
  );

  initial begin
    $dumpfile("dump.vcd");
    $dumpvars(0, testbench);
    
    $display("Creating waveform file...");
    
    x = 0; y = 0; #10;
    x = 0; y = 1; #10;
    x = 1; y = 0; #10;
    x = 1; y = 1; #10;
    
    $finish;
  end
endmodule

Dumpvars Level Examples

Level	What Gets Dumped
`0`	All signals in the module and all sub-modules
`1`	Only signals in the specified module (not sub-modules)

Challenge

Add the missing $dumpfile and $dumpvars statements to create a waveform file.

What to do:

Add $dumpfile to create a file named waveform.vcd
Add $dumpvars to dump all signals in the testbench module

Cheat sheet

Use $dumpfile and $dumpvars inside an initial block to generate a VCD (Value Change Dump) waveform file for viewing in tools like GTKWave:

initial begin
  $dumpfile("dump.vcd");   // creates the VCD file
  $dumpvars(0, testbench); // dumps all signals in testbench and sub-modules
end

$dumpvars(level, module_name) levels:

0 — all signals in the module and all sub-modules
1 — only signals in the specified module (no sub-modules)

Try it yourself

module and_gate (
  input a,
  input b,
  output c
);
  assign c = a & b;
endmodule

module testbench;
  reg a, b;
  wire c;
  
  and_gate dut (
    .a(a),
    .b(b),
    .c(c)
  );

  initial begin
    // TODO: Add $dumpfile to create "waveform.vcd"
    
    
    // TODO: Add $dumpvars to dump all signals in testbench
    // Hint: $dumpvars(0, testbench);
    
    if ($test$plusargs("vcd")) begin
        $display("VCD file created successfully");
    end
    
    $display("Simulation running...");
    
    a = 0; b = 0; #10;
    a = 0; b = 1; #10;
    a = 1; b = 0; #10;
    a = 1; b = 1; #10;
    
    $display("Simulation complete. Open waveform.vcd");
    $finish;
  end
endmodule