Verifying The Output

Part of the Fundamentals section of Coddy's Verilog journey — lesson 83 of 90.

Challenge

In this lesson, you will add waveform dump commands and verify that the traffic light controller works correctly.

What to do:

Update the testbench to:

Add $dumpfile to create a waveform file named traffic.vcd
Add $dumpvars to dump all signals in the testbench
Run the simulation and check the waveform

Try it yourself

module traffic_light (
  input clk,
  input reset,
  output reg red,
  output reg yellow,
  output reg green
);
  // States: 0=Green, 1=Yellow, 2=Red
  reg [1:0] state;
  reg [5:0] counter;
  
  always @(posedge clk or posedge reset) begin
    if (reset) begin
      state <= 2;      // Start at Red
      counter <= 0;
    end else begin
      if (counter == 0) begin
        // Change state
        if (state == 0) begin  // Green -> Yellow
          state <= 1;
          counter <= 10;       // Yellow lasts 10 seconds
        end else if (state == 1) begin  // Yellow -> Red
          state <= 2;
          counter <= 40;       // Red lasts 40 seconds
        end else begin  // Red -> Green
          state <= 0;
          counter <= 30;       // Green lasts 30 seconds
        end
      end else begin
        counter <= counter - 1;
      end
    end
  end
  
  // Output logic
  always @(*) begin
    red = (state == 2);
    yellow = (state == 1);
    green = (state == 0);
  end
  
endmodule

module testbench;
  reg clk, reset;
  wire red, yellow, green;
  
  traffic_light uut (
    .clk(clk),
    .reset(reset),
    .red(red),
    .yellow(yellow),
    .green(green)
  );
  
  always #1 clk = ~clk;
  
  initial begin
    // TODO: Add $dumpfile to create "traffic.vcd"
    
    // TODO: Add $dumpvars to dump all signals (0, testbench)
    
    $display("Traffic Light Test");
    $monitor("Time %0t: red=%b, yellow=%b, green=%b", $time, red, yellow, green);
    
    clk = 0;
    reset = 1;
    #2 reset = 0;
    
    #90;
    $finish;
  end
endmodule