Module Instantiation

Part of the Fundamentals section of Coddy's Verilog journey — lesson 33 of 90.

Module instantiation is the process of creating a copy of a module inside another module. It is how you build larger designs by connecting smaller components together.

Once you have defined a module, you can use it inside another module. This is called instantiation. Each instantiation creates a separate instance of that module. Think of it like using a blueprint to build multiple copies of the same component.

Basic Syntax

module_name instance_name (connections);

Part	Meaning
`module_name`	Name of the module to instantiate
`instance_name`	Unique name for this copy
`connections`	Signals connected to the module's ports

Simple Example

Step 1: Define a module

module and_gate (
  input a,
  input b,
  output c
);
  assign c = a & b;
endmodule

Step 2: Instantiate it in another module

module top (
  input x,
  input y,
  output z
);
  and_gate gate1 (x, y, z);
endmodule

Here is what happens in this code:

and_gate — the name of the module we want to use (must exist somewhere)
gate1 — a unique name we give to this specific instance
(x, y, z) — the signals we connect to the module's ports (in the same order they appear in the module definition)

The first signal x connects to the first port a. The second signal y connects to the second port b. The third signal z connects to the third port c.

You must pass signals to the module. The parentheses cannot be empty. The number of signals must match the number of ports.

Multiple Instances

You can create multiple copies of the same module:

module top;
  wire out1, out2;
  wire sig1, sig2, sig3, sig4;
  
  and_gate gate1 (sig1, sig2, out1);
  and_gate gate2 (sig3, sig4, out2);
endmodule

Each instance has its own name (gate1, gate2) and its own connections. They work independently.

What Happens During Instantiation

A copy of the hardware is created
Each instance has its own set of signals
Instances run in parallel (simultaneously)

The signals you pass determine how instances connect to the rest of your design

Rules for Instantiation

Rule	Why
Instance name must be unique	To distinguish between copies
Module name must exist	Must be defined elsewhere
Number of connections must match number of ports	Otherwise Verilog doesn't know what connects where
Connection order must match port order	First signal connects to first port, etc.

Challenge

Complete the code by instantiating the or_gate module.

What to do:

Instantiate or_gate with instance name or1
Pass the signals in the correct order: input_a, input_b, output_y

Cheat sheet

Module instantiation creates a copy of a module inside another module:

module_name instance_name (connections);

Example:

module and_gate (input a, input b, output c);
  assign c = a & b;
endmodule

module top (input x, input y, output z);
  and_gate gate1 (x, y, z); // x→a, y→b, z→c
endmodule

Rules:

Instance name must be unique
Number of connections must match number of ports
Connection order must match port definition order
Multiple instances run in parallel, each with its own signals

Try it yourself

module or_gate (
  input in1,
  input in2,
  output result
);
  assign result = in1 | in2;
endmodule

module top (
  input input_a,
  input input_b,
  output output_y
);
  
  // TODO: Instantiate or_gate with name or1
  // Pass signals in order: input_a, input_b, output_y
  // Do not use .port(signal) syntax
  

endmodule