Comments

Part of the Fundamentals section of Coddy's Verilog journey — lesson 5 of 90.

Comments are notes in your code that the computer ignores. They help explain what your code does.

1. Single-line comment

// This is a single-line comment
assign c = a & b;  // Comments can go after code too

Everything after // is ignored by the computer.

2. Multi-line comment

/* This is a multi-line comment
   It can span several lines
   Useful for longer explanations */
assign c = a & b;

Everything between /* and */ is ignored.

Challenge

In this challenge, you need to add comments to an existing module.

What to do:

Add a single-line comment at the top explaining what the module does
// This is a module called 'test'
Add a multi-line comment at the end of the code explaining what the counter does
/*
* It has a clock input, a reset input,
* and a 4-bit output called count.
* The initial block prints a message
* to show that comments are ignored.
*/

Cheat sheet

Comments in Verilog are ignored by the compiler and used to explain code.

Single-line comment — everything after // is ignored:

// This is a comment
assign c = a & b;  // Inline comment

Multi-line comment — everything between /* and */ is ignored:

/* This spans
   multiple lines */
assign c = a & b;

Try it yourself


module test(
  input clk,
  input reset,
  output reg [3:0] count
);

  initial $display("Comments are ignored by the computer");
  
endmodule

Test yourself

This lesson includes a short quiz. Start the lesson to answer it and track your progress.

1Introduction

4Operators Part 1

7Assign And Gates

10Decision Making

13Timing And Delays

16Final Challenges