Display And Monitor
Part of the Fundamentals section of Coddy's Verilog journey — lesson 75 of 90.
$display and $monitor are system tasks used to print information from your simulation. They help you see what is happening inside your design.
$display
$display prints a message once at the moment it is executed.
Syntax:
$display("message", variables);Example:
initial begin
$display("Simulation started");
#10;
$display("Time 10");
#10;
$display("Time 20");
endOutput:
Simulation started
Time 10
Time 20$monitor
$monitor prints a message automatically whenever any of its variables change.
Syntax:
$monitor("message", variables);Example:
initial begin
a = 0; b = 0;
$monitor("Time %0t: a=%b, b=%b", $time, a, b);
#10 a = 1;
#10 b = 1;
#10 a = 0;
endOutput:
Time 0: a=0, b=0
Time 10: a=1, b=0
Time 20: a=1, b=1
Time 30: a=0, b=1$display vs $monitor
| $display | $monitor | |
|---|---|---|
| When it prints | Once when executed | Every time a variable changes |
| How many times | As many times as you call it | Continuously (until changed) |
| Use for | Headers, test messages | Tracking changing signals |
Common Format Specifiers
| Specifier | Meaning | Example |
|---|---|---|
%b | Binary | $display("%b", a); |
%d | Decimal | $display("%d", count); |
%h | Hexadecimal | $display("%h", data); |
%t | Time | $display("%t", $time); |
%0t | Time (no spaces) | $display("%0t", $time); |
%s | String | $display("%s", "Hello"); |
Important Rules
| Rule | Explanation |
|---|---|
$display prints once | Good for headers and final results |
$monitor prints on change | Good for watching signals |
Only one $monitor active | Last one overrides previous |
Use $finish to stop | Otherwise simulation may run forever |
Challenge
Add the missing $display and $monitor statements to this testbench.
What to do:
- Add
$displayto print a header: "Testing OR Gate" - Add
$monitorto print time, x, y, and z whenever any signal changes. Format: "Time %0t: x=%b, y=%b, z=%b" - Add
$displayat the end to print "Test complete"
Cheat sheet
$display prints once when executed; $monitor prints automatically whenever any of its variables change.
$display("message", variables);
$monitor("message", variables);Example:
initial begin
$display("Simulation started");
$monitor("Time %0t: a=%b, b=%b", $time, a, b);
#10 a = 1;
#10 b = 1;
endCommon format specifiers:
%b— Binary%d— Decimal%h— Hexadecimal%t/%0t— Time (with/without padding)%s— String
Key rules:
- Only one
$monitoris active at a time — the last one overrides previous ones. - Use
$finishto stop the simulation.
Try it yourself
module or_gate (
input x,
input y,
output z
);
assign z = x | y;
endmodule
module testbench;
reg x, y;
wire z;
or_gate dut (
.x(x),
.y(y),
.z(z)
);
initial begin
// TODO: Add $display header "Testing OR Gate"
// TODO: Add $monitor to track time, x, y, z
// Format: "Time %0t: x=%b, y=%b, z=%b"
// Apply stimulus
x = 0; y = 0; #10;
x = 0; y = 1; #10;
x = 1; y = 0; #10;
x = 1; y = 1; #10;
// TODO: Add $display "Test complete"
$finish;
end
endmoduleThis lesson includes a short quiz. Start the lesson to answer it and track your progress.
All lessons in Fundamentals
4Operators Part 1
Arithmetic OperatorsModulo OperatorComparison OperatorsRecap - Simple MathBitwise Operators7Assign And Gates
Continuous AssignmentAssign With OperatorsBuilt In Gate PrimitivesAND OR NOT GatesXOR XNOR GatesRecap - Logic Gate Circuit10Decision Making
If StatementIf - ElseRecap - Simple ComparatorCase StatementCasex And CasezRecap - ALU Design5Operators Part 2
Logical OperatorsReduction OperatorsShift OperatorsConcatenation OperatorConditional OperatorRecap - Operator Challenge14Testbench Basics
What Is A TestbenchCreating StimulusDisplay And MonitorDumpfile And DumpvarsUsing System TasksRecap - Full Testbench3Number System
Binary RepresentationSized NumbersUnsized NumbersNegative NumbersSpecial Values X And ZRecap - Number Formats6Modules
Module StructureInput And Output PortsInout PortsModule InstantiationPort Mapping By NamePort Mapping By OrderRecap - Build A Module9Procedural Blocks
Always BlockInitial BlockSensitivity ListBlocking AssignmentNon Blocking AssignmentRecap - Always vs Initial15Traffic Light Controller
Defining The StatesState Machine Logic