Initial Block

Part of the Fundamentals section of Coddy's Verilog journey — lesson 47 of 90.

Verilog has two procedural blocks: initial (runs once) and always (runs continuously). Now let's cover the initial block.

What is an Initial Block?

The initial block runs only once at the beginning of simulation (time 0). When it finishes, it does not run again.

It is mainly used in testbenches for:

Setting initial values
Generating test signals
Displaying messages
Starting the simulation

Syntax

initial begin
  // Statements execute once, in sequence
end

Basic Example

initial begin
  $display("Simulation started");
  $display("This runs once");
  $finish;
end

Output:

Simulation started
This runs once

Using Initial Block for Test Signals

initial begin
  a = 0;
  #10 a = 1;
  #10 a = 0;
  #10 $finish;
end

This changes a at times: 0, 10, and 20.

Initial vs Always

	`initial`	`always`
Runs	Once	Continuously (forever)
Use for	Testbenches, initialization	Hardware (flip-flops, counters)
Synthesizable?	No (simulation only)	Yes (with sensitivity list)

Important Notes

initial blocks are not synthesizable — they cannot be turned into hardware
Use initial only in testbenches
Without $finish, the simulation will run forever (no clock to stop it)

Challenge

Add the missing initial block that sets a to 0, then after 10 time units sets a to 1.

What to do:

Add initial begin and end
Set a = 0
Wait #10
Set a = 1
Add $finish to end simulation

Cheat sheet

The initial block runs once at simulation time 0. Used only in testbenches (not synthesizable).

initial begin
  a = 0;       // set at time 0
  #10 a = 1;   // set at time 10
  #10 a = 0;   // set at time 20
  $finish;     // end simulation
end

Without $finish, the simulation runs forever.

	`initial`	`always`
Runs	Once	Continuously
Use for	Testbenches	Hardware
Synthesizable?	No	Yes

Try it yourself

module test;
  reg a;
  
  // TODO: Add initial block here
  // Set a = 0
  // Wait #10
  // Set a = 1
  // Add $finish; to end simulation
  
endmodule