Reg Type

Part of the Fundamentals section of Coddy's Verilog journey — lesson 7 of 90.

Reg is the second main data type in Verilog. Unlike wire, a reg stores a value. It is a variable that holds its value until something changes it.

reg can store values
reg is used in always blocks
reg does NOT mean "register" in hardware—it just means “storage”

Declaring a reg

reg x;           // Single-bit reg
reg y, z;        // Multiple regs on one line

How reg Works

module reg_example;
  reg x;
  
  initial begin
    x = 0;           // x becomes 0
    $display("x = %d", x);  // Prints: x = 0
    
    x = 1;           // x becomes 1
    $display("x = %d", x);  // Prints: x = 1
  end
endmodule

Challenge

What to do:

Add a reg called count

Cheat sheet

reg stores a value and holds it until changed. Used inside always or initial blocks.

reg x;       // Single-bit reg
reg y, z;    // Multiple regs

initial begin
  x = 0;  // assign value
  x = 1;  // update value
end

Try it yourself

module counter(
  input clk,
  input reset,
  output out   // wire by default (remove reg)
);
  
  // Declare reg count here

  
endmodule

Test yourself

This lesson includes a short quiz. Start the lesson to answer it and track your progress.

All lessons in Fundamentals

1Introduction

What Is Verilog Hardware vs Software Design Abstraction Levels Your First Module Comments

4Operators Part 1

Arithmetic Operators Modulo Operator Comparison Operators Recap - Simple Math Bitwise Operators

7Assign And Gates

Continuous Assignment Assign With Operators Built In Gate Primitives AND OR NOT Gates XOR XNOR Gates Recap - Logic Gate Circuit

10Decision Making

If Statement If - Else Recap - Simple Comparator Case Statement Casex And Casez Recap - ALU Design

13Timing And Delays

What Are Delays Gate Delays Assignment Delays Timescale Directive Clock Generation Recap - Timing Control

16Final Challenges

4 Bit Counter Decoder Design Shift Register