Module Structure

Part of the Fundamentals section of Coddy's Verilog journey — lesson 30 of 90.

A module is the basic building block in Verilog. Every design is built from modules that connect together to form larger systems.

A module is a hardware component with:

A name
Inputs (signals coming in)
Outputs (signals going out)
Internal logic (what the module does)

Think of a module as a chip with pins and internal circuitry.

Basic Module Structure

Every module follows this structure:

module module_name (
  input  signals,
  output signals
);
  
  // Internal declarations (wires, regs, etc.)
  // Logic (assign statements, always blocks, etc.)
  
endmodule

Parts of a Module

Part	Purpose
`module` keyword	Starts the module definition
`module_name`	Name of the module
`( )`	List of input and output ports
`input` / `output`	Declare port direction
Module body	Internal logic and connections
`endmodule`	Ends the module definition

Simple Module Example

module and_gate (
  input a,
  input b,
  output c
);
  assign c = a & b;
endmodule

This module:

Is named and_gate
Has two inputs (a, b)
Has one output (c)
Contains one assign statement defining the logic

Rules for Module Structure

One module per file is common practice
Module name should describe its function
Ports are listed between parentheses after the name

Inputs are always input (cannot be written inside)
Outputs are output (can be reg or wire)
<strong>endmodule</strong> must close the module

Challenge

Fill the missing parts to complete this module.

What to do:

Add the module name my_and
Add input for x
Add input for y
Add output for z
Add the internal logic using assign

Cheat sheet

A module is the basic building block in Verilog — a hardware component with inputs, outputs, and internal logic.

module module_name (
  input  a,
  input  b,
  output c
);
  // Internal logic
  assign c = a & b;

endmodule

module / endmodule — start and end the definition
input — signal coming in (read-only inside module)
output — signal going out (can be reg or wire)
assign — defines combinational logic

Try it yourself

module ______ (   // Add module name
  ______ x,       // Add input
  ______ y,       // Add input
  ______ z        // Add output
);
  // Add assign statement here (z = x & y)
  
endmodule